Semiconductor memory device and semiconductor device

A semiconductor memory device formed on a semiconductor substrate to which at least a plurality of control clock signals and a plurality of address signals are externally applied, comprising:

• a plurality of input terminals provided corresponding to said plurality of control block signals and said plurality of address signals, respectively;
• a first power supply line provided common to said plurality of input terminals, to which a first power supply potential is applied;
• a second power supply line provided common to said plurality of input terminals, to which a second power supply potential is applied;
• a first well region of a first conductivity type formed at a surface of said semiconductor substrate corresponding to each of the input terminals, having a potential fixed region connected to said first power supply line;
• second and third well regions formed at a surface of each of the first well regions and each having a potential fixed region connected to said second power supply line;
• and
• internal protecting means provided corresponding to each of the input terminals including a field transistor of the first conductivity type formed at a surface of the corresponding one of the second well regions and a diffused resistance element of the first conductivity type formed at a surface of the corresponding one of the third well regions and having distance between an input side end and the potential fixed region of said first well region set to be not smaller than a prescribed value, for protecting inner portion from a surge current flowing to the corresponding input terminal.

A semiconductor memory device formed on a semiconductor substrate, to which at least a plurality of control block signals and a plurality of address signals are applied externally, comprising:

• a plurality of input terminals provided corresponding to said plurality of control block signals and said plurality of address signals, respectively;
• a first power supply line provided common to said plurality of input terminals, to which a first power supply potential is applied;
• a second power supply line provided common to said plurality of input terminals, to which a second power supply potential is applied;
• a first well region of a first conductivity type formed at a surface of said semiconductor substrate corresponding to each of said input terminals, having a potential fixed region formed to have a columnar shape from the surface to an inner portion, said potential fixed region being connected to said first power supply line;
• second and third well regions formed at a surface of said first well region corresponding to each of the input terminals, each having a potential fixed region connected to said second power supply line;
• and
• internal protecting means provided corresponding to each of the input terminals, including a field transistor of the first conductivity type formed at a surface of the corresponding one of the second well regions and a diffused resistance element of the first conductivity type formed at a surface of the corresponding one of the third well regions, for protecting an inner portion from a surge current flowing to the corresponding input terminal.

The semiconductor memory device formed on a semiconductor substrate, to which at least a plurality of control clock signals and a plurality of address signals are applied externally, comprising:

• a plurality of input terminals provided corresponding to said plurality of control clock signals and said plurality of address signals, respectively;
• a first power supply line provided common to said plurality of input terminals, to which a first power supply potential is applied;
• a second power supply line provided common to said plurality of input terminals, to which a second power supply potential is applied;
• a resistance element provided corresponding to each of the input terminals;
• a first well region of a first conductivity type formed at a surface of said semiconductor substrate corresponding to each of the input terminals, and having a potential fixed region connected said first power supply line through the corresponding one of the resistance elements;
• second and third well regions of a second conductivity type formed at a surface of said first well region corresponding to each of the input terminals, each having a potential fixed region connected to said second power supply line;
• and
• internal protecting means provided corresponding to each of the input terminals and including a field transistor of the first conductivity type formed at a surface of the corresponding one of the second well regions and a diffused resistance element of the first conductivity type formed at a surface of the corresponding one of the third well regions, for protecting an inner portion from a surge current flowing to the corresponding input terminal.

A semiconductor memory device formed on a semiconductor substrate, to which at least a plurality of control clock signals and a plurality of address signals are applied externally, comprising:

• a plurality of input terminals provided corresponding to said plurality of control clock signals and said plurality of address signals, respectively;
• a first power supply line provided common to said plurality of input terminals, to which a first power supply potential is applied;
• a second power supply line provided common to said plurality of input terminals, to which a second power supply potential is applied;
• a first well region of a first conductivity type formed at a surface of said semiconductor substrate corresponding to each of the input terminals, and having a potential fixed region connected to said first power supply line;
• and
• a second well region of a second conductivity type formed at a surface of each of the first well regions, and having a potential fixed region connected to said second power supply line;
• and
• internal protecting means provided corresponding to each of the input terminals and including a field transistor of the first conductivity type formed at a surface of the corresponding one of the second well regions and a diffused resistance element of the first conductivity type, for protecting an inner portion from a surge current flowing to the corresponding input terminal.

A semiconductor memory device formed on a semiconductor substrate, to which at least a plurality of control clock signals and a plurality of address signals are applied externally, comprising:

• a plurality of input terminals provided corresponding to said plurality of control clock signals and said plurality of address signals, respectively, and divided into one or more groups;
• a first upper power supply line provided common to said plurality of input terminals, to which a first power supply potential is applied;
• a second upper power supply line provided common to said plurality of input terminals, to which a second power supply potential is applied;
• a lower power supply line provided corresponding to each group of the input terminals;
• a first well region of a first conductivity type formed at a surface of said semiconductor substrate corresponding to each group of the input terminals, and having a potential fixed region connected to said first upper power supply line only through a corresponding one of the lower power supply lines;
• second and third well regions provided at a surface of the corresponding one of the first well regions corresponding to each input terminal, each having a potential fixed region connected to the second upper power supply line;
• and
• internal protecting means provided corresponding to each of the input terminals, and including a field transistor of the first conductivity type formed at a surface of the corresponding one of the second well regions and a diffused resistance element of the first conductivity type formed at a surface of the corresponding one of the third well regions, for protecting an inner portion from a surge current flowing into the corresponding input terminal.

A semiconductor memory device formed on a semiconductor substrate, to which at least a plurality of control clock signals and a plurality of address signals are applied externally, comprising:

• a plurality of input terminals provided corresponding to said plurality of control clock signals and said plurality of address signals respectively, and divided into one or more groups;
• a first power supply line provided common to said plurality of input terminals, to which a first power supply potential is applied;
• a second power supply line provided common to said plurality of input terminals, to which a second power supply potential is applied;
• a first well region of a first conductivity type formed at a surface of said semiconductor substrate corresponding to each group of the input terminals, having a potential fixed region connected to said first power supply line;
• second and third well regions of a second conductivity type formed at a surface of the corresponding one of the first well regions corresponding to each input terminal, each having a potential fixed region connected to said second power supply line;
• and
• internal protecting means provided corresponding to each input terminal and including a field transistor of the first conductivity type formed at a surface of the corresponding one of the second well regions and a diffused resistance element of the first conductivity type formed at a surface of the corresponding one of the third well regions, for protecting an inner portion from a surge current flowing to the corresponding input terminal.

A semiconductor memory device formed on a semiconductor substrate, comprising:

• an input terminal to which a signal is input externally;
• an internal circuitry performing a prescribed operation in response to the signal input to said input terminal;
• internal protecting means including a diffused resistance element formed at a surface of said semiconductor substrate and connected to said input terminal and to said internal circuitry by means of a metal interconnection, for protecting said internal circuitry from a surge current flowing to said input terminal;
• and
• an impurity diffused well region formed in the surface of the substrate and having lower impurity concentration than said diffused resistance element, said impurity diffused well region being formed at least at a position corresponding to a contact portion between said diffused resistance element and said metal interconnection, in a portion of the semiconductor substrate below said diffused resistance element of said internal protecting means.

A semiconductor device formed on a semiconductor substrate, comprising:

• an input terminal to which a signal is input externally;
• an internal circuitry performing a prescribed operation in response to the signal input to said input terminal;
• internal protecting means formed at a surface of said semiconductor substrate and including a first impurity diffused resistance region connected to said input terminal and to said internal circuitry by a metal interconnection, for protecting said internal circuitry from a surge current flowing to said input terminal;
• and
• a second impurity resistance region formed separated from said first impurity diffused resistance region of said internal protecting means, to which a fixed potential is applied.

A semiconductor memory device formed on a semiconductor substrate, comprising:

• an input terminal to which a signal is input externally;
• an internal circuitry performing a prescribed operation in response to the signal input to said input terminal;
• an internal protecting means including a first impurity diffused resistance region formed at a surface of said semiconductor substrate, for protecting said internal circuitry from a surge current input to said input terminal;
• and
• a second impurity diffused region formed at a surface of said first impurity diffused resistance region of said internal protecting means having higher impurity concentration than said first impurity diffused resistance region and connected to said input terminal and said internal protecting means by a metal interconnection.

A semiconductor device formed on a semiconductor substrate, comprising:

• an input terminal to which a signal is input externally;
• an internal protecting means for protecting an inner portion from a surge current flowing to said input terminal;
• an internal circuitry including a first impurity diffused region formed at a surface of the semiconductor substrate and connected to said input terminal by a metal interconnection, responsive to a signal input to said input terminal for performing a prescribed operation;
• and
• a second impurity diffused region formed in the semiconductor substrate and having higher impurity concentration than said first impurity diffused region, formed at least at a portion corresponding to a contact portion between said first impurity diffused region and said metal interconnection in a portion of the semiconductor substrate below said first impurity diffused region of said internal circuitry.

A semiconductor device formed on a semiconductor substrate, comprising:

• an input terminal to which a signal is input externally;
• internal protecting means for protecting an inner portion from a surge current input to said input terminal;
• an internal circuitry including a first impurity diffused region formed at a surface of the substrate and connected to said input terminal by a metal interconnection responsive to a signal input to said input terminal for performing a prescribed operation;
• and
• a second impurity diffused region formed at the surface of the substrate separated from said first impurity diffused region of said internal circuitry, to which a fixed potential is applied.

A semiconductor device formed on a semiconductor substrate, comprising:

• an input terminal to which a signal is externally input;
• an internal circuitry performing a prescribed operation in response to a signal input to said input terminal;
• and
• internal protecting means including a first well region formed in the substrate and having a conductivity type different from that of said semiconductor substrate, a first impurity diffused region of the same conductivity type as said semiconductor substrate formed at a surface of said well region and connected to said input terminal and to said internal circuitry, a second well region formed in the semiconductor substrate and having a conductivity type different from that of said semiconductor substrate, and a second impurity diffused region having the same conductivity type as said semiconductor substrate, formed at a surface of said second well region, to which a fixed potential is applied, for protecting said internal circuitry from a surge current input to said input terminal.