Data read circuit of a memory
AssigneeLG Semicon Co., Ltd.
InventorsSang Hyun Lee, Ha Min Sung
Life of this patent
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Abstract
A data read circuit of a memory includes an inverting unit, a precharging unit, a first amplifying unit, a second amplifying unit, and an output buffer unit. The inverting unit inverts data from a sense amplifier, and the precharging unit precharges a data bus line to Vcc/2. The first amplifying unit receives and amplifies the inverted data, and the second amplifying unit is commonly connected to an input terminal of the first amplifying unit to receive and amplify the signal output from the inverting unit. The output buffer unit receives, inverts and outputs the signal amplified by the first and second amplifying units.
Claims9
A data read circuit of a memory comprising:
- an inverting unit having an input and an output, said input receiving data;
- a precharging unit precharging a data bus line coupled to said output of said inverting unit to substantially one half a power supply voltage;
- a first amplifying unit coupled to said output of said inverting unit to amplify said output of said inverting unit, said first amplifying unit having an output;
- a second amplifying unit coupled to said input of said inverting unit to amplify said output from said inverting unit, said second amplifying unit having an output;
- and
- an output buffer unit coupled to invert and amplify said outputs of said first and second amplifying units.
A data read circuit of a memory, comprising:
- an inverting unit having an input and an output, said input receiving data;
- a precharging unit precharging a data bus line coupled to said output of said inverting unit to substantially one half a power supply voltage;
- a first amplifying unit coupled to said output of said inverting unit to differentially amplify said output of said inverting unit, said first amplifying unit having an output;
- a second amplifying unit coupled to said output of said inverting unit to differentially amplify said output of said inverting unit, said second amplifying unit having an output;
- and
- an output buffer unit coupled to invert and amplify said outputs of said first and second amplifying units.
Dependencies are inferred from the claim text.