Semiconductor memory device and high-voltage switching circuit

A semiconductor memory device comprising;

• an array of electrically rewritable memory cells which are arranged in a matrix;
• erasing means for applying an erasing voltage to said memory cells to effect erasing;
• and
• writing means for applying a writing voltage to said memory cells to effect writing;
• said erasing means and writing means comprising a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising,
• a first MOS transistor having a gate, a source, and a drain coupled to said input terminal,
• a second MOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first MOS transistor, and
• a third MOS transistor having a gate, a source coupled to the source of said first MOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode,
• wherein said first, second and third MOS transistors are of the same conductivity type, the gates of said first and second MOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first MOS transistor to said source of said second MOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third MOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode.

A semiconductor memory device comprising:

• an array of electrically rewritable memory cells which are arranged in a matrix;
• erasing means for applying an erasing voltage to said memory cells to effect erasing;
• and
• writing means for applying a writing voltage to said memory cells to effect writing;
• said erasing means and writing means comprising a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising,
• a first MOS transistor having a gate, a source, and a drain coupled to said input terminal,
• a second MOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first MOS transistor, and
• a third MOS transistor having a gate, a source coupled to the source of said first MOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode,
• wherein said first, second and third MOS transistors are of the same conductivity type, the gates of said first and second MOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first MOS transistor to said source of said second MOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third MOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode said first, second and third MOS transistors composed of two types of MOS transistors, a first type and a second type,
• the second-type MOS transistor being an n-channel MOS transistor that is in an inversion state with the substrate bias voltage at 0 V and the gate and source voltages at a predetermined third voltage and in a cut-off state with the substrate bias voltage and gate voltage at 0 V and the source voltage at a predetermined fourth voltage, and
• the first-type MOS transistor being an n-channel MOS transistor that is in a weak inversion state or an inversion state with the substrate bias voltage, gate voltage, and source voltage at 0 V and having a threshold voltage higher than that of said second-type n-channel MOS transistor.

A semiconductor memory device comprising:

• an array of electrically rewritable memory cells which are arranged in a matrix;
• erasing means for applying an erasing voltage to said memory cells to effect erasing;
• and
• writing means for applying a writing voltage to said memory cells to effect writing;
• said erasing means and writing means comprising one of MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied and MOS transistors which transfer a voltage higher than said erasing voltage and writing voltage and containing MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage 0 V.

A semiconductor memory device comprising:

• an array of electrically rewritable memory cells which are arranged in a matrix;
• erasing means for applying an erasing voltage to said memory cells to effect erasing;
• and
• writing means for applying a writing voltage to said memory cells to effect writing;
• and
• said erasing means and writing means comprising either MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than said erasing voltage and writing voltage composed only of MOS transistors of a first type, said MOS transistors being in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

A semiconductor memory device comprising:

• an array of electrically rewritable memory cells which are arranged in a matrix;
• erasing means for applying an erasing voltage to said memory cells to effect erasing;
• and
• writing means for applying a writing voltage to said memory cells to effect writing;
• and
• said erasing means and writing means comprising either MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than said erasing voltage and writing voltage being composed of two types of MOS transistors, a first type and a second type,
• the second-type MOS transistor being an n-channel MOS transistor that is in an inversion state with the substrate bias voltage at 0 V and the gate and source voltages at a power-supply voltage and in a cut-off state with the substrate bias voltage and gate voltage at 0 V and the source voltage at the power-supply voltage, and
• the first-type MOS transistor being an n-channel MOS transistor that is in a weak inversion state or an inversion state with the substrate bias voltage, gate voltage, and source voltage at 0 V and having a threshold voltage higher than that of said second-type n-channel MOS transistor.