US 5,708,604 AGranted

Dynamic selection control in a memory

AssigneeSGS-Thomson Microelectronics S.A.

InventorsMarco Fontana, Luigi Pascucci

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Abstract

A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.

Claims10

Dependent claims

A driving circuit for a pull-up device for an input node of a final selection stage of a memory line capable of producing a relatively fast increment of pull-up current during a selection phase and a relatively fast decrement of pull-up current during a deselection phase, said driving circuit comprising:

a charge pump circuit for generating a first voltage;
level shifting means supplied with the first voltage generated internally by said charge pump circuit and driven by an impulse produced by a switching in address circuitry of the memory and capable of generating a pair of complementary control signals of an amplitude similar to that of said first voltage;
and
means driven by the pair of complementary control signals and comprising at least one charge redistribution capacitance switchable to a driving node of the pull-up device for causing a fast voltage drop on the driving node during a selection phase and a slow increment of voltage on said driving node during a deselection phase, said means comprising
a first charge transistor functionally connected between a supply rail and the driving node of the pull-up device;
a second discharge transistor functionally connected between said capacitance and the ground node, driven in phase with said first charge transistor by a first signal of said pair of complementary control signals;
and
a switch, driven by the other of said pair of complementary control signals, capable of coupling the capacitance to the driving node.

5 more elements

level shifting means supplied with the first internally generated voltage and driven by an impulse produced by a switching in address circuitry of the memory and capable of generating a pair of complementary control signals of an amplitude similar to that of said first voltage;
and
means driven by the pair of complementary control signals and comprising at least one charge redistribution capacitance switchable to a driving node of the pull-up device for causing a fast voltage drop on the driving node during a selection phase and a slow increment of voltage on said driving node during a deselection phase, said means comprising
a first n-channel charge transistor functionally connected between a supply rail and the driving node of the pull-up device;
a second n-channel discharge transistor functionally connected between said capacitance and the ground node, driven in phase with said first charge transistor by a first signal of said pair of complementary control signals;
and
a switch, driven by the other of said pair of complementary control signals, capable of coupling the capacitance to the driving node.

4 more elements

Dependencies are inferred from the claim text.