US 5,708,603 AGranted

Semiconductor memory device

AssigneeSharp Kabushiki Kaisha

InventorKatsuji Tanaka

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Abstract

An object of the invention is to vary data width by changing over the readout mode, to change over the number of operating sense amplifiers in order to minimize the readout current, and to reduce the power consumption. A switch circuit operates only half of sense amplifiers by a first EN1 signal when the output data width is set at 8 bits by data width control signal BYTE. At this time, other sense amplifiers are not put in action, and hence the power consumption is saved. When the external output is 16 bits, all sense amplifiers are put in operation. Besides, in the case of internal readout operation such as verification by internal state signal RUN, all sense amplifiers are operated to perform an efficient high speed operation.

Claims5

Dependent claims

A semiconductor memory device having a number of sense amplifiers and a number of memory elements arranged in an array having a width equal to a predetermined maximum number of bits, the number of sense amplifiers equal to the predetermined maximum number, said sense amplifiers coupled to said memory elements, said memory device comprising:

width setting means for setting data width for external output to be within a range of the maximum number of bits;
and
control means coupled to said sense amplifiers and said width setting means, said control means for operating only sense amplifiers corresponding to the set data width, in response to an output from the width setting means;
wherein the memory device has a function of readout operation for internal output different from readout operation for external output;
wherein the control means operates all sense amplifiers in readout operation for internal output;
wherein the readout operation for internal output is a verification operation of verifying contents stored in the memory element.

3 more elements

Dependencies are inferred from the claim text.