Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device

Apparatus for identifying redundancy memory cells that are selected to replace defective memory cells of a memory matrix that includes at least one memory sector and that communicates with a data bus and an address bus that has a sector address portion, the apparatus comprising:

• a first redundancy address register that is associated with a first one of said redundancy memory cells and is operable to store an unprogrammed state until said first redundancy address register is programmed with an address of a first one of said defective memory cells that is located in a first sector of said matrix, said first sector having a first sector address;
• a control circuit that is operable to generate a check signal during a check mode;
• a first select circuit that is coupled to said control circuit and to said first redundancy address register and that is operable to generate a first unprogrammed-detect signal in response to said check signal when said first redundancy address register contains said unprogrammed state;
• and
• a multiplexer circuit that is coupled to said first select circuit, said data bus, and said control circuit, and that is operable to couple said first unprogrammed-detect signal to said data bus in response to said check signal.

A method for pointing out redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus, the method comprising:

• storing a default state in a redundancy address register that is associated with one of said redundancy memory cells until said redundancy address register is programmed with an address of one of said defective memory cells;
• generating a default-detect signal during a check-number mode if said redundancy address register contains said default state;
• and
• coupling said default-detect signal to said data bus during said check-number mode.

A method for identifying redundancy memory cells that are selected to replace defective memory cells of a memory matrix that includes at least one memory sector and that communicates with a data bus and an address bus that has a sector address portion, the method comprising:

• storing in a first redundancy address register that is associated with a first one of said redundancy memory cells an unprogrammed state until said first redundancy address register is programmed with an address of a first one of said defective memory cells that is located in a first sector of said matrix, said first sector having a first sector address;
• generating a check signal during a check mode;
• generating a first unprogrammed-detect signal in response to said check signal when said first redundancy address register contains said unprogrammed state;
• and
• coupling said first unprogrammed-detect signal to said data bus.

A memory circuit, comprising:

• an address bus;
• a data bus;
• a memory matrix having at least one sector of memory cells, and having redundancy memory cells that are operable to replace defective ones of said memory cells;
• redundancy address registers each associated with one of said redundancy memory cells and each operable to store an unprogrammed state until programmed with an address of one of said defective memory cells;
• a control circuit that is operable to generate a check-number signal during a check-number mode of the memory circuit;
• a plurality of selection circuits each coupled to said control circuit and to an associated one of said redundancy address registers, each selection circuit operable to generate a redundancy selection signal
• when said check-number signal is present and said unprogrammed state occupies said associated one of said redundancy address registers, and
• when said check-number signal is absent and an address of a defective memory cell that occupies said associated one of said redundancy address registers also occupies said address bus;
• and
• a data-bus multiplexer coupled to said control circuit, said data bus, and said selection circuits, said multiplexer operable to couple said redundancy selection signals to said data bus when said check-number signal is present, said multiplexer operable to couple contents of addressed memory and redundancy memory cells to said data bus when said check-number signal is absent.

Apparatus for identifying redundancy memory cells that are programmed to replace defective memory cells of a memory matrix that communicates with a data bus and an address bus, the apparatus comprising:

• a control circuit that is operable to generate during a redundancy-check mode a redundancy-check signal having a first state;
• a redundancy address register that is associated with a respective one of said redundancy memory cells;
• a guard cell that is operable to store an unprogrammed state until said redundancy address register is programmed with an address of one of said defective memory cells;
• and
• a data-bus multiplexer that is coupled to said guard storage cell, said data bus, and said control circuit, said data-bus multiplexer operable to couple said guard cell to said data bus in response to said first state of said redundancy-check signal.

A memory device, comprising:

• an address bus having one or more address bits;
• a data bus;
• a memory matrix having at least one sector of memory cells, and having redundancy memory cells that are operable to replace defective ones of said memory cells;
• a control circuit that is operable to generate a check-number signal having a first value during a check-number mode of said memory device;
• redundancy address registers that are coupled to said address bus and that are each associated with one of said redundancy memory cells;
• a plurality of guard cells that are each associated with one of said redundant address registers, that each store an unprogrammed state before said associated redundancy address register is programmed with an address of one of said defective memory cells, and that each store a programmed state after said associated redundancy address register is programmed with said address;
• and
• a data-bus multiplexer that is coupled to said guard cells, said data bus, and said control circuit, said data-bus multiplexer operable to couple said guard cells to said data bus in response to said first value of said check-number signal.