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US 5,708,599 AGranted
Semiconductor memory device capable of reducing power consumption
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHirotoshi Sato, Kunihiko Kozaru
Life of this patent
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Abstract
A reference voltage generated in a Vref1 generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is selected by a column decoder. On the other hand, a substrate voltage generated in a Vbb generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is not selected by the column decoder.
Claims13
A semiconductor memory device, comprising:
- a static memory cell array having a plurality of columns;
- column selecting means for selecting one of said columns of said static memory cell array;
- substrate voltage generating means for generating a substrate voltage;
- reference voltage generating means for generating a reference voltage;
- and
- voltage supplying means for supplying said reference voltage to a backgate of an access transistor in each static memory cell constituting the selected column and supplying said substrate voltage to a backgate of an access transistor in each static memory cell constituting non-selected columns.
3 more elements
A semiconductor memory device, comprising:
- a plurality of word lines;
- a plurality of bit line pairs intersecting said word lines;
- a plurality of static memory cells provided corresponding to respective intersections of said word lines and said bit line pairs, each static memory cell including first and second access transistors and first and second driver transistors;
- a column decoder responsive to a column address signal for generating a plurality of column selection signals respectively corresponding to said bit line pairs;
- a plurality of column select gates respectively provided corresponding to said bit line pairs, each column select gate being connected to a corresponding bit line pair and responsive to a corresponding activated column selection signal for being turned on;
- substrate voltage generating means for generating a substrate voltage;
- reference voltage generating means for generating a reference voltage;
- and
- a plurality of voltage supplying means respectively provided corresponding to said bit line pairs, each voltage supplying means being responsive to a corresponding column selection signal applied to a corresponding column select gate for supplying said reference voltage to respective backgates of said first and said second access transistors in said each static memory cell connected to a corresponding bit line pair when said column selection signal is activated, and supplying said substrate voltage to respective backgates of said first and said second access transistors in said each static memory cell connected to said corresponding bit line pair when said column selection signal is deactivated.
6 more elements
Dependencies are inferred from the claim text.