US 5,708,598 AGranted

System and method for reading multiple voltage level memories

OwnerTamio Saitoinventor

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Abstract

A system and method for reading multi-bit memory cells. The invention resides in employing a plurality of comparators to compare the voltage contained in a multi-bit memory cell with a reference voltage, where each comparator is associated with a single pair of bit lines. For each pair of bit lines, a first bit line is coupled to a multi-bit memory cell and a second bit line is coupled to a dummy cell containing a reference voltage. The first bit line is also coupled to a data bus. The data bus is configured to connect the first bit line to a first input of each of a plurality of comparators that are associated with other bit lines and memory cells. Each comparator has a unique reference voltage applied to its second input. Each comparator compares the voltage on the first bit line with the applied reference voltage and outputs the result of this comparison to a controller. The controller repeatedly instructs a voltage source to alter the voltage levels applied to the second input of each comparator until the controller can determine the values of the data bits represented by the voltage stored in the multi-bit memory cell.

Claims16

Dependent claims

The method of reading a first multi-bit memory cell, comprising the steps of:

(1) generating a first reference voltage on a first bit line and a second reference voltage on a second bit line;
(2) coupling a third bit line to an input of a first comparator and an input of a second comparator, said first comparator associated with said first bit line and the first multi-bit memory cell and said second comparator associated with said second bit line and a second multi-bit memory cell;
(3) outputting a first memory voltage, representing a plurality of data bits, from the first multi-bit memory cell to said third bit line;
(4) comparing said first memory voltage with said first reference voltage and said, second reference voltage, simultaneously, using said first comparator and said second comparator;
(5) determining said bit value for one or more of said data bits based upon a result of said comparison step, if one or more of said data bit values can be determined;
(6) generating a third reference voltage on said first bit line and a fourth reference voltage on said second bit line based upon the previous comparison result, if all of said data bit values have not been determined;
(7) comparing said first memory voltage with said third reference voltage and said fourth reference voltage, simultaneously, if all of said data bit values have not been determined;
(8) determining a value for one or more of said data bits based upon the result of the previous comparison steps, if one or more of said data bit values can be determined, and if all of said data bit values have not been previously determined;
and
(9) repeating steps (6) through (8) until determining a data bit value for all of said data bits.

7 more elements

A computer memory system comprising:

a first bit line;
a second bit line;
a first data line, removably coupled to said first bit line and removably coupled to said second bit line;
a first multi-bit memory cell, coupled to said first bit line, for storing a first voltage representing a plurality of first cell data bits;
a second multi-bit memory cell, coupled to said second bit line, for storing a second voltage representing a plurality of second cell data bits;
a first comparator, having a first input removably coupled to one of said first bit line and said first data line, a second input, and a first output, for comparing a voltage on said first input with a voltage on said second input;
a second comparator, having a third input removably coupled to one of said second bit line and said first data line, a fourth input, and a second output, for comparing a voltage on said third input with a voltage on said fourth input.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/597,515Filed 6 Jun 1996 · continuation
Priority: 24 Apr 1995
Granted: 13 Jan 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 11/56
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor: using storage elements…
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/565
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using capacitive charge…

Family

Serial428,781Parent of this continuation · filed 24 Apr 1995
US 5,708,598 AThis patent

From the US filing history. Foreign family members aren’t listed.

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