Filter circuit
AssigneeUniden Corporation
InventorShigeo Sato
Life of this patent
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Abstract
A filter circuit comprises a 1-bit quantizer, a first moving average type of filter having an N-dimensional 1-bit delay element operating in synchronism to a clock of a first sampling frequency, a thinning circuit for thinning an output from the first moving average type of filter in synchronism to a clock of a second sampling frequency, and a second moving average type of filter having an M-order q-bit delay element operating in synchronism to a clock of a second sampling frequency, wherein the thinning circuit removes anti-alias elements in the second moving average type of filter.
Claims15
A filter circuit comprising:
- a first moving average type of filter having an N-dimensional 1-bit delay element (N;
- A positive integer) receiving a 1-bit quantized signal and executing sequential operations in synchronism to a clock of a first sampling frequency;
- a thinning circuit for thinning an output from said first moving average type of filter in synchronism to a clock of a second sampling frequency;
- and
- a second moving average type of filter having an M-order q-bit delay element (M, q:
- Positive integers) receiving an output from said thinning circuit and executing sequential operations in synchronism to a clock of said second sampling frequency;
- wherein said thinning circuit removes anti-alias elements of said second moving average type of filter, namely signal elements each having a frequency higher than a half of said second sampling frequency.
A filter circuit for a selective call receiver for detecting a base band signal from a received signal and decoding transmitted data comprising:
- a 1-bit quantizer for subjecting said base band signal to 1-bit quantization;
- a first moving average type of filter having an N-dimensional 1-bit delay element (N:
- Positive integer) receiving an output from said 1-bit quantizer and executing sequential operations in synchronism to a clock of the first sampling frequency;
- a thinning circuit for subjecting an output from said first moving average type of filter to a thinning processing in synchronism to a clock of the second sampling frequency;
- and
- a second moving average type of filter having an M-order q-bit delay element (M, q:
- Positive integers) receiving an output from said thinning circuit and executing sequential operations in synchronism to a clock of the second sampling frequency;
- wherein said thinning circuit removes anti-alias elements of said second moving average type of filter, namely signal elements each having a frequency higher than one-half of said second sampling frequency.
A digital filter system comprising:
- a first low-pass filter responsive to a digital input signal for forming a first filtered signal and having a first delay element controlled by a first clock signal at first sampling frequency for sequentially delaying said input signal in synchronism with said first clock signal;
- a thinning circuit coupled to said first low-pass filter ad having at least one register circuit controlled by said first clock signal for producing a sample of said first filtered signal in synchronism with said first clock signal, and an adder controlled by a second clock signal at second sampling frequency for summing said first filtered signal with said produced sample in synchronism with said second clock signal;
- and
- a second low-pass filter coupled to said thinning circuit and having a second delay element for sequentially delaying an output signal of said adder in synchronism with said second clock signal.
Dependencies are inferred from the claim text.