Automatic instruction string generation method and device for verifying processor operation model and logic

An automatic instruction string generation device for verifying an operation model and logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic instruction string generation device comprising:

• specification information holding means for holding specification information about the configuration of the pipeline of the processor and each instruction executed by the processor;
• operation model configuring means for configuring the operation model which represents the operation of the pipeline based on the specification information held by said specification information holding means and represents states of components of the pipeline and a transition relation of the states using a plurality of state variables;
• test state listing means for listing test states of a plurality of states of the state variables contained in the operation model configured by said operation model configuring means;
• and
• test instruction string generating means for generating a test instruction string for a process in which a state of the operation model configured by said operation model configuring means indicates a transition from an initial state to each of the test states listed by said test state listing means.

An automatic processor operation model generating device for generating an operation model of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the process, said automatic processor operation model generating device comprising:

• specification information holding means for holding specification information about the configuration of the pipeline of the processor and each instruction executed by the processor;
• operation model configuring means for configuring an initial operation model which represents the operation of the pipeline based on the specification information held by said specification information holding means and represents states of components of the pipeline and a transition relation of the states using a plurality of state variables;
• and
• state number minimizing means for configuring a minimized operation model by minimizing based on attitudes of the states of the components of the pipelines, a number of states of each of the state variables through a grouping process performed on the states of each of the state variables contained in the initial operation model configured by said initial operation model configuring means.

An automatic logic verification test instruction string generating method for verifying logic used in a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting input information defining an operation model which represents the operation of the pipeline and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and the input information also defining at least one test state in which a conflict occurs among a plurality of state variables contained in the operation model;
• listing test instruction strings for processes in which a state of the operation model indicates a transition from a predetermined input state to any test state held in said input information holding means without including conflict causing states of the state variables forming the operation model;
• and
• repeating a process of calculating a next time state which is reached after the states of the state variables forming the operation model enter a new test state of a listed test instruction string, and listing the test instruction strings with the next time state set as the predetermined input state.

An automatic logic verification test instruction string generating device for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for holding input information defining an operation model which represents the operation of the pipeline and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and the input information also defining at least one test state in which a conflict occurs among a plurality of state variables contained in the operation model;
• test instruction string listing means for listing test instruction strings for processes in which a state of the operation model indicates a transition from a predetermined input state to any test state held in said input information holding means without including conflict causing states of the state variables forming the operation model and held in said input information holding means;
• and
• next time state calculating means for calculating a next time state reached after the states of the state variables forming the operation model enter a test state of one of the test instruction strings listed by said test instruction string listing means, and listing the test instruction strings with the next time state set as the predetermined input state.

An automatic logic verification test instruction string generation method for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting input information defining an operation model which represents the operation of the pipeline and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and the input information also defining a state evaluation function having as input a plurality of state variables contained in the operation model;
• listing attainable states, reached from an initial state of the state variables forming the operation model, when a value of the state evaluation function satisfies a predetermined condition;
• and
• listing instruction strings reaching one of the attainable states as test instruction strings.

An automatic logic verification test instruction generating device for verifying logic used in a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for holding input information defining an operation model which represents the operation of the pipeline and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and input information also defining a state evaluation function having as input a plurality of state variables contained in the operation model;
• attainable state listing means for listing attainable states, reached from an initial state of the state variables forming the operation model, when a value of the state evaluation function satisfies a predetermined condition;
• and
• test instruction string listing means for listing instruction strings reaching one of the attainable states listed by said attainable state listing means as test instruction strings.

An automatic logic verification test instruction string generation method for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting input information defining an operation model which represents the operation of the pipeline and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and the input information also defining a state evaluation function having as input a plurality of state variables contained in the operation model;
• listing states reached from an initial state of the state variables forming the operation model;
• calculating a value of the state evaluation function for a listed state;
• listing instruction strings reaching the listed state;
• selecting a state in which a calculated value satisfies a predetermined condition from listed states;
• selecting an instruction string for a selected state from listed instruction strings;
• and
• selecting a selected instruction string as a test instruction string.

An automatic logic verification test instruction generating device for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for holding as input information the operation model which represents the operation of the pipeline and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also holding as input information a state evaluation function having as input a plurality of state variables contained in the operation model;
• attainable state listing means for listing states reached from an initial state of a plurality of state variables forming the operation model input as the input information;
• state evaluation function calculating means for calculating a value of the state evaluation function for a listed state listed by said attainable state listing means;
• test instruction string listing means for listing instruction strings reaching a state listed by said attainable state listing means;
• and
• test instruction output means for selecting a state in which a value calculated by said state evaluation function calculating means satisfies a predetermined condition from states listed by said attainable state listing means, selected an instruction string for a selected state from instruction strings listed by said instruction string listing means, and outputting a selected instruction string as a test instruction string.

An automatic logic verification test instruction string generation method for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information a state time series of a plurality of state variables contained in the operation model;
• listing state time series reached from an initial state of a plurality of state variables forming the operation model input as the input information, said state time series being input as the input information;
• and
• listing instruction strings realizing listed state time series as test instruction strings.

An automatic logic verification test instruction generating device for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for holding as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information a state time series of a plurality of state variables contained in the operation model;
• attainable state time series listing means for listing state time series reached from an initial state of a plurality of state variables forming the operation model input as the input information, said state time series being input as the input information;
• and
• test instruction string listing means for listing instruction strings realizing state time series listed by said attainable state time series listing means as test instruction strings.

An automatic logic verification test instruction string generation method for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information a state time series of a plurality of state variables contained in the operation model;
• listing states reached from an initial state of a plurality of state variables forming the operation model input as the input information;
• listing instruction strings reaching a listed state;
• retrieving a state time series matching the state time series input as the input information while tracing back the state time series from the listed state;
• selecting an instruction string reaching a last state of a retrieved state time series from listed instruction strings;
• and
• outputting a selected instruction string as a test instruction string.

An automatic logic verification test instruction string generating device for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for holding as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information a state time series of a plurality of state variables contained in the operation model;
• attainable state listing means for listing states reached from an initial state of a plurality of state variables forming the operation model input as the input information;
• instruction string listing means for listing instruction strings reaching a state listed by said attainable state listing means;
• state time series retrieving means for retrieving a state time series matching the state time series input as the input information while tracing back the state time series from the state listed by said attainable state listing means;
• and
• test instruction string output means for selecting an instruction string reaching a last state of a state time series retrieved by said state time series retrieving means from listed instruction strings listed by said instruction string listing means, and outputting a selected instruction string as a test instruction string.

An automatic logic verification test instruction string generation method for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information an evaluation function of a state time series of a plurality of state variables contained in the operation model;
• listing state time series reached from an initial state of a plurality of state variables forming the operation model input as the input information, a value of said evaluation function of the state time series satisfying a predetermined condition;
• and
• listing instruction strings realizing listed state time series as test instruction strings.

An automatic logic verification test instruction generating device for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for inputting as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information an evaluation function of a state time series of a plurality of state variables contained in the operation model;
• attainable state time series listing means for listing state time series reached from an initial state of a plurality of state variables forming the operation model input as the input information, a value of said evaluation function of the state time series satisfying a predetermined condition;
• and
• test instruction string listing means for listing instruction strings realizing state time series listed by said attainable state time series listing means as test instruction strings.

An automatic logic verification test instruction string generation method for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction string generation method comprising:

• inputting as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information an evaluation function of a state time series of a plurality of state variables contained in the operation model;
• listing states reached from an initial state of a plurality of state variables forming the operation model input as the input information;
• listing instruction strings reaching a listed state;
• calculating the evaluation function for state time series obtained by tracing back the state time series from the listed states;
• selecting time series of states in which a calculated value satisfies a predetermined condition from the state time series obtained by tracing back the state time series from the listed states;
• selecting an instruction string reaching a last state of a selected state time series from listed instruction strings;
• and
• outputting a selected instruction string as a test instruction string.

An automatic logic verification test instruction generating device for verifying logic of a processor in which an operation of a pipeline is represented based on specification information about a configuration of the pipeline of the processor and each instruction executed by the processor, said automatic logic verification test instruction generating device comprising:

• input information holding means for inputting as input information the operation model which represents the operation of the pipeline, and represents states of components of the pipeline and a transition relation among the states using a plurality of state variables, and also inputting as input information an evaluation function of a state time series of a plurality of state variables contained in the operation model;
• attainable state listing means for listing states reached from an initial state of a plurality of state variables forming the operation model input as the input information;
• instruction string listing means for listing instruction strings reaching a state listed by said attainable state listing means;
• state time series evaluation function calculating means for calculating the evaluation function for state time series obtained by tracing back the state time series from the states listed by said attainable state listing means;
• and
• test instruction string output means for selecting time series of states in which a value calculated by said state time series evaluation function calculating means satisfies a predetermined condition from the state time series obtained by tracing back from the state time series obtained by tracing back the state time series from the states listed by said attainable state listing means, selecting an instruction string reaching a last state of a selected state time series from instruction strings listed by said instruction string listing means, and outputting a selected instruction string as a test instruction string.