Coherent sampling digitizer system

An apparatus for digitizing an input signal of frequency F.sub.t, the apparatus comprising:

• means for generating a master clock signal of frequency F.sub.MCLK, that is other than an integer multiple of F.sub.t ;
• first means receiving the master clock signal for sampling the input signal N times during M consecutive cycles of the input signal at a rate F.sub.MCLK /K, where M and N are integers greater than one and for digitizing each sample to produce an N-term output data sequence;
• and
• second means for finding and supplying to said first means an appropriate integer value for K for which the N-term data sequence produced by said first means has a data content most nearly approximates input signal magnitudes at times evenly distributed over one cycle of the input signal.

A method for periodically sampling an input signal of frequency F.sub.t in response to an input clock signal of frequency F.sub.MCLK, the method comprising the steps of:

• (a) searching a Farey series of limited order to find and select a Farey series number P/Q within said Farey series approximating F.sub.t /F.sub.MCLK, where P and Q are relatively prime integers;
• (b) computing an integer factor Q.sub.i of Q;
• (c) frequency dividing the input clock signal by an integer K=Q*J/Q.sub.i, where J is an integer greater than 0, to produce a periodic timing signal;
• and
• (d) successively sampling said input signal at a rate controlled by said timing signal.

A method for digitizing an input signal of frequency F.sub.t in response to an input clock signal of frequency F.sub.MCLK, the method comprising the steps of:

• (a) searching a Farey series of limited order to find and select a Farey series number P/Q within said Farey series approximating F.sub.t /F.sub.MCLK, where P and Q are relatively prime integers;
• (b) computing an integer factor Q.sub.i of Q;
• (c) frequency dividing the input clock signal by an integer K=Q*J/Q.sub.i, where J is an integer greater than 0, to produce a periodic timing signal;
• and
• (d) digitizing said input signal at a rate controlled by said timing signal.