Frequency multiplying device and digitally-controlled oscillator

A frequency multiplier comprising:

• multi-phase clock generating means for generating a plurality of clock signals having phases shifted relative to one another;
• encoding means for encoding a timing of a predetermined cycle portion of said reference signal with a cycle of one of said plurality of clock signals as a resolution;
• and
• output means for generating a pulse at a predetermined timing and at a frequency which is a multiple of a frequency of said reference signal based on said encoded timing, with a phase-differential time of one of said plurality of clock signals as a control portion resolution.

A digitally-controlled oscillator for generating a pulse having a clock cycle corresponding to externally-applied multi-bit digital data, said oscillator comprising:

• a multi-phase clock for generating a plurality of clock signals whose phases are shifted relative to one another;
• coarse time calculating means for calculating a coarse timing corresponding to a most significant bit portion of said data with one of said plurality of clock signals being taken as a resolution;
• fine time calculating means for calculating a phase-differential fine timing corresponding to a least significant bit portion of said data based on a phase differential time of said plurality of clock signals;
• and
• output means for outputting a pulse having a cycle timing which is a total of said coarse timing and said fine timing.

A digitally-controlled oscillator for generating a pulse having a clock cycle corresponding to externally-applied digital data, said oscillator comprising:

• a ring oscillator including a plurality of inverters;
• output means for generating an output pulse;
• coarse control means for coarsely controlling said output means so that a cycle time of said output pulse corresponds to a most significant portion of said data, an output pulse cycle from said ring oscillator being used as a time resolution;
• and
• fine control means for finely controlling said output means so that a cycle time of said output pulse corresponds to a least significant portion of said data, a phase differential among said inverters being used as a time resolution.

A digitally controlled oscillator comprising:

• a pulse circulation circuit, including a plurality of inverters connected in a ring configuration, for generating a plurality of pulse signals having a predetermined phase differential therebetween;
• counting means for counting pulse signals output from a predetermined inverter in said plurality of inverters and for determining when a count thereof is equal to an externally-applied value;
• pulse detecting means for receiving data representative of a sequence of phases on a given one of said plurality of pulse signals and, after said counting means determines that said count has reached said externally-applied value, detecting that a particular pulse signal corresponding to input data has been output from said pulse circulation circuit;
• output means for outputting a predetermined signal when said pulse detecting means detects that said pulse signal corresponding to said input data has been output;
• updating means for outputting digital data as new input data of said pulse detecting means when a detecting operation of said pulse detecting means has been terminated once, said digital data representative of an addition of said data representative of said sequence of phases and current input data of said pulse detecting means;
• modifying means for incrementing said value used by said counting means when a value of digital data output by said updating means exceeds a number of pulse signals output from said pulse circulation circuit;
• wherein said plurality of pulse signals output by said pulse circulation circuit are divided into a predetermined plurality of groups ordered starting with signals having earlier phases with said particular pulse signal being used as a reference;
• said pulse detecting means includes
• detection signal outputting means for outputting a plurality of detection signals respectively corresponding to said plurality of groups of pulse signals being asserted in an interval until all pulse signals of corresponding groups are continuously output from said pulse circulation circuit,
• a plurality of latches, respectively corresponding to said plurality of detection signals, for generating an output signal when a pulse signal is input while a corresponding detection signal is asserted, and
• selecting means for selecting a pulse signal from said plurality of pulse signals output by said pulse circulation circuit in correspondence with said input data and for providing said selected pulse signal to a latch in said plurality of latches which is provided with input pulse signals corresponding to a group to which said pulse signal belongs;
• and
• said output means is for outputting said predetermined signal responsive to an asserted output from any of said latches.

A digitally controlled oscillator comprising:

• a pulse circulation circuit, including a plurality of inverters connected in a ring configuration, for generating a plurality of pulse signals having a predetermined phase differential therebetween;
• counting means for counting pulse signals output from a predetermined inverter in said plurality of inverters and for determining when a count thereof is equal to an externally-applied value;
• pulse detecting means for receiving data representative of a sequence of phases on a given one of said plurality of pulse signals and, after said counting means determines that said count has reached said externally-applied value, detecting that a particular pulse signal corresponding to input data has been output from said pulse circulation circuit;
• output means for outputting a predetermined signal when said pulse detecting means detects that said pulse signal corresponding to said input data has been output;
• updating means for outputting digital data as new input data of said pulse detecting means when a detecting operation of said pulse detecting means has been terminated once, said digital data representative of an addition of said data representative of said sequence of phases and current input data of said pulse detecting means;
• modifying means for incrementing said value used by said counting means when a value of digital data output by said updating means exceeds a number of pulse signals output from said pulse circulation circuit;
• wherein said plurality of pulse signals output by said pulse circulation circuit are divided into a predetermined plurality of groups ordered starting with signals having earlier phases with said particular pulse signal being used as a reference;
• said pulse detecting means includes
• detection signal outputting means for outputting a plurality of detection signals respectively corresponding to said plurality of groups of pulse signals being asserted in an interval until all pulse signals of corresponding groups are continuously output from said pulse circulation circuit,
• a plurality of latches, respectively corresponding to said plurality of detection signals, for generating an output signal when a pulse signal is input while a corresponding detection signal is asserted,
• first selecting means for selecting a plurality of pulse signals which are candidates from said groups of pulse signals in correspondence with a first portion of said input data, and for providing said selected pulse signals to a latch in said plurality of latches which is provided with input pulse signals corresponding to a group to which said pulse signal belongs, and
• second selecting means for alternatively selecting an output of a latch circuit in correspondence with a second portion of said input data;
• and
• said output means is for outputting said predetermined output signal when an output of said second selecting means is asserted.

A digitally controlled oscillator comprising:

• a pulse circulation circuit, including a plurality of inverters connected in a ring configuration, for generating a plurality of pulse signals having a predetermined phase differential therebetween;
• counting means for counting pulse signals output from a predetermined inverter in said plurality of inverters and for determining when a count thereof is equal to an externally-applied value;
• pulse detecting means for receiving data representative of a sequence of phases on a given one of said plurality of pulse signals and, after said counting means determines that said count has reached said externally-applied value, detecting that a particular pulse signal corresponding to input data has been output from said pulse circulation circuit;
• output means for outputting a predetermined signal when said pulse detecting means detects that said pulse signal corresponding to said input data has been output;
• updating means for outputting digital data as new input data of said pulse detecting means when a detecting operation of said pulse detecting means has been terminated once, said digital data representative of an addition of said data representative of said sequence of phases and current input data of said pulse detecting means;
• modifying means for incrementing said value used by said counting means when a value of digital data output by said updating means exceeds a number of pulse signals output from said pulse circulation circuit;
• wherein said plurality of pulse signals output by said pulse circulation circuit are divided into a predetermined plurality of groups ordered starting with signals having earlier phases with said particular pulse signal being used as a reference;
• said pulse detecting means includes
• detection signal outputting means for outputting a plurality of detection signals respectively corresponding to said plurality of groups of pulse signals being asserted in an interval until all pulse signals of corresponding groups are continuously output from said pulse circulation circuit, and
• a plurality of latches, corresponding to respective ones of said plurality of pulse signals output from said pulse circulation circuit, for generating an output signal when a pulse signal is input while a corresponding pulse is asserted;
• and
• said output means is for outputting said predetermined output signal when an output of said plurality of latches is asserted.