Fast 3-state booster-circuit
AssigneeAdvanced Micro Devices, Inc.
InventorsLee E. Cleveland, Johnny C. Chen
Life of this patent
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Abstract
A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.
Claims20
A voltage booster circuit for generating at a wordline supply node a supply voltage boosted to be higher than a power supply potential for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and program modes of operation, comprising:
- precharging transistor means (Pl10) responsive to a precharge signal for selectively connecting the power supply potential to the wordline supply node;
- charge pump means (114) responsive to an enable signal for pumping up the wordline supply node to a higher wordline supply voltage defining a program level during a programming mode;
- driver circuit means (117) for selectively generating a 3-state output voltage at an output node to drive a booster capacitor (115);
- said booster capacitor being interconnected between said output node of said driver circuit means and said wordline supply node;
- said driver circuit means generating said 3-state output voltage which is at a low state during a precharge mode, at a high state during a read mode, and at a high impedance state during the programming mode;
- said driver circuit means effectively disconnecting said booster capacitor from said wordline supply node when said 3-state output voltage is at the high impedance state so as to reduce the capacitive loading on said charge pumping means;
- and
- said pumping means boosting subsequently the wordline supply node to the program level after the output node of said driver circuit means is in the high impedance state.
A voltage booster circuit for generating at a wordline supply node a supply voltage boosted to be higher than a power supply potential for driving wordlines which have a reduction in voltage variations at the wordline supply node and have less power dissipation, comprising:
- precharging transistor means (Pl10) responsive to a precharge signal for selectively connecting the power supply potential to the wordline supply node;
- charge pump means (114) responsive to an enable signal for pumping up the wordline supply node to a higher wordline supply voltage defining a program level during a programming mode;
- a plurality of booster capacitors (115a, 115b) each having a first end and a second end, each of said first end of said plurality of booster capacitors being connected to said wordline supply node;
- a plurality of driver circuits (117a, 117b) each selectively generating a 3-state output voltage at an output node, each output node being connected to a corresponding one of said second end of said plurality of booster capacitors;
- each of said plurality of driver circuits generating said 3-state output voltage which is at a low state during a precharge mode, at a high state during a read mode, and at a high impedance state during the programming mode;
- each of said plurality of driver circuits effectively disconnecting said associated booster capacitor from said wordline supply node when said 3-state output voltage is at the high impedance state so as to reduce the capacitive loading on said charge pumping means;
- and
- said pumping means boosting subsequently the wordline supply node to the program level after the output node of said driver circuit means is in the high impedance state.
A voltage booster circuit for generating at a wordline supply node a supply voltage boosted to be higher than a power supply potential for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and program modes of operation, comprising:
- precharging transistor means (Pl10) responsive to a precharge signal for selectively connecting the power supply potential to the wordline supply node;
- charge pump means (114) responsive to an enable signal for pumping up the wordline supply node to a higher wordline supply voltage defining a program level during a programming mode;
- a first driver circuit (117a) for selectively generating a 3-state output voltage at an output node to drive a first booster capacitor (115a);
- a second driver circuit (117b) for selectively generating a 3-state output voltage at an output node to drive a second booster capacitor (115b);
- said first booster capacitor (115a) being interconnected between said output node of said first driver circuit and said wordline supply node;
- said second booster capacitor (115b) being interconnected between said output node of said second driver circuit and said wordline supply node;
- a voltage detector circuit (117c) for generating a detected signal;
- and
- said second driver circuit being responsive to said detected signal for causing its output to be at a high impedance state during the programming mode so as to reduce the capacitive loading on said charge pump means.
Dependencies are inferred from the claim text.