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US 5,708,384 AGranted
Computational circuit
AssigneesYozan Inc., Sharp Kabushiki Kaisha
InventorsGuoliang Shou, Sunao Takatori, Makoto Yamamoto
Life of this patent
Estimating the term…
Abstract
A computational circuit which has a capacitive coupling for weighted addition. Addition is performed by the capacitive coupling. By connecting and disconnecting capacitances of the capacitive coupling, multiplication can be executed by changing the weights of the capacitors. An inverter with a feed back capacitance is connected to a computational circuit to improve the accuracy of the computation. Capacitances consist of unit capacitances of scattered distribution, so that the deviation of the capacities is minimized.
Claims19
A computational circuit comprising:
- a capacitive coupling having a plurality of capacitors, each capacitor in said plurality of capacitors having an input and an output, said outputs of said plurality of capacitors being connected at all times during operation of said computational circuit to a common output;
- and
- a plurality of switching circuits receiving an analog input voltage and a set of digital data defined by bits of digital data, each switching circuit in said plurality of switching circuits being associated with one capacitor in said plurality of capacitors and with one bit of digital data in said set of digital data, each switching circuit selectively connecting said input of said associated capacitor to one of said analog input voltage and ground in response to said bit of digital data associated with that switching circuit, said capacitors in said plurality of capacitances having capacitance values corresponding to weights to be placed on said analog input voltage such that each capacitor, responsive to being connected to said analog input voltage, weights said analog input voltage by a selected weighting factor, said set of digital data being provided to said plurality of switching circuits such that a total weighting factor applied to said analog input voltage is selected by said bits of digital data, thereby multiplying said analog input voltage by said set of digital data.
A computational circuit comprising:
- a plurality of sample/hold portions sequentially connected, wherein each said sample/hold portion comprises:
- an input switch to which an analog voltage is input:
- an input capacitance sequentially connected to said input switch;
- a first amplifier sequentially connected to said input capacitance at all times during operation of said computational circuit;
- an intermediate switch sequentially connected to said first amplifier;
- an intermediate capacitance sequentially connected to said intermediate switch;
- a second amplifier sequentially connected to said intermediate capacitance at all times during operation of said computational circuit;
- a first feed back capacitance connecting an output of said first amplifier to an input of said first amplifier;
- and
- a second feed back capacitance connecting an output of said second amplifier to an input of said second amplifier;
- and
- a plurality of computational portions each receiving an output of one of said sample/hold portions.
9 more elements
A computational circuit comprising:
- a plurality of sample/hold portions sequentially connected, wherein each said sample/hold portion comprises:
- a first operational amplifier receiving an analog input voltage at a non-inverted input;
- a first switch connected to an output of said first operational amplifier;
- a second operational amplifier connected to a non-inverted input through said first switch to said output of said first operational amplifier;
- a second switch connected to an output of said second operational amplifier;
- a first capacitance having a first terminal connected through said first switch to said output of said first operational amplifier and a second terminal connected to ground;
- a second capacitance having a first terminal connected through said second switch to said output of said second operational amplifier and a second terminal connected to ground;
- a first feed back line connecting said first terminal of said first capacitance to an inverted input of said first operational amplifier;
- and
- a second feed back line connecting said second terminal of said second capacitance to an inverted input of said second operational amplifier;
- and
- a plurality of computational portions each receiving an output of one of said sample/hold portions.
9 more elements
A computational circuit comprising:
- a plurality of sample/hold portions connected sequentially, wherein each said sample/hold portion comprises:
- a first switch connected to an analog input voltage at a first terminal;
- a first capacitance connected through said first switch to said analog input voltage;
- a plurality of first inverters connected sequentially to said first capacitance at all times during operation of said computational circuit;
- a second switch sequentially connected to one of said first inverters;
- a second capacitance having a first and a second terminal, said second capacitance being connected to said second switch by said first terminal;
- a plurality of second inverters connected sequentially to said second terminal of said second capacitance at all times during operation of said computational circuit;
- a first feed back capacitance connecting an output of said first inverter to an input of said first inverter;
- and
- a second feed back capacitance connecting an output of said second inverter to an input of said second inverter;
- and
- a plurality of computational portions each receiving an output of one of said sample/hold portions.
9 more elements
A computational circuit comprising:
- a plurality of sample/hold portions sequentially connected, wherein each said sample/hold portion comprises:
- a first switch having a first input terminal, a first and a second output terminal, said first input terminal receiving an analog input voltage and said switch selectively connecting said first input terminal to one of said first output terminal and said second output terminal;
- a first capacitance sequentially connected to said first output terminal of said first switch;
- a second capacitance sequentially connected to said second output terminal of said first switch;
- a plurality of first inverters sequentially connected to said first capacitance;
- a plurality of second inverters sequentially connected to said second capacitance;
- a second switch having a first input terminal, a second input terminal and a first output terminal, said first input terminal of said second switch being connected to an output of said plurality of first inverters, said second input terminal of said second switch being connected to an output of said plurality of second inverters, said second switching selectively connecting one of said first input terminal and said second input terminal thereof to said first output terminal of said second switch;
- a third capacitance connected to said first output terminal of said second switch;
- a third inverter sequentially connected to said third capacitance;
- a first feed back capacitance connecting an output of said plurality of first inverters to an input of said plurality of first inverters;
- a second feed back capacitance connecting an output of said plurality of second inverters to an input of said plurality of second inverters;
- and
- a third feed back capacitance connecting an output of said third inverters to an input of said third inverter;
- and
- a computational portion receiving an output of one of said sample/hold portions.
12 more elements
A computational circuit comprising:
- a plurality of sample/hold portions sequentially connected;
- and
- a plurality of computational portions each receiving an output of one of said sample/hold portions, wherein sequential computation is performed by each of said computational portions, each computational portion comprising:
- a plurality of capacitances each of which has a different capacitance value, said plurality of capacitances receiving said output of said one of said sample/hold portions and outputs of said plurality of capacitances being connected at all time during operation of said computational circuit to a common output;
- a plurality of switches each of which is provided for selectively connecting said output of said one of said sample/hold portions to one or more of said capacitances;
- and
- a digital signal containing parallel data for controlling said plurality of switches.
4 more elements
Dependencies are inferred from the claim text.