Integrated circuit frequency controlled modulator for use in a phase lock loop

A circuit for modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M, comprising:

• N number of multiplier circuits, each multiplier circuit having multiply means for multiplying one phase of the first waveform with one phase of the second waveform and for generating first and second currents having a difference which is proportional to a product of the one phase of the first waveform and the one phase of the second waveform;
• and
• a load circuit, coupled to the multiplier circuits, having a first node into which the first currents generated by each of the multiplier circuits are summed together to form a first summation current and a second node into which the second currents generated by each of the multiplier circuits are summed together to form a second summation current, the load circuit having a comparing stage for comparing which of the first and second summation currents is larger and for generating a first clock signal having a frequency approximately equal to a frequency of a change in magnitude of the first and second summation currents;
• wherein the comparing stage of the load circuit includes,
• a first transistor coupled to the first node for conducting a first portion of the first summation current;
• a second transistor coupled to the second node for conducting a first portion of the second summation current;
• and
• a current difference amplifier coupled to the first and second transistors for converting a difference between the first portion of the first summation current and the first portion of the second summation current into the first clock signal;
• wherein the current difference amplifier includes,
• a third transistor having a gate coupled to a gate of the first transistor and forming a first current mirror with the first transistor;
• a fourth transistor having a gate coupled to a gate of the second transistor and forming a second current mirror with the second transistor;
• a fifth transistor having a drain coupled to a drain of the third transistor;
• and
• a sixth transistor having a drain coupled to a drain of the fourth transistor and a gate coupled to a gate of the fifth transistor and forming a third current mirror with the fifth transistor, wherein the first clock signal is generated at the drains of the fourth and sixth transistors.

A circuit for modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M, comprising:

• N number of multiplier circuits, each multiplier circuit having multiply means for multiplying one phase of the first waveform with one phase of the second waveform and for generating first and second currents having a difference which is proportional to a product of the one phase of the first waveform and the one phase of the second waveform;
• and
• a load circuit, coupled to the multiplier circuits, having a first node into which the first currents generated by each of the multiplier circuits are summed together to form a first summation current and a second node into which the second currents generated by each of the multiplier circuits are summed together to form a second summation current, the load circuit having a comparing stage for comparing which of the first and second summation currents is larger and for generating a first clock signal having a frequency approximately equal to a frequency of a change in magnitude of the first and second summation currents;
• wherein the comparing stage of the load circuit includes,
• a first transistor coupled to the first node for conducting a first portion of the first summation current;
• a second transistor coupled to the second node for conducting a first portion of the second summation current;
• a current difference amplifier coupled to the first and second transistors for converting a difference between the first portion of the first summation current and the first portion of the second summation current into the first clock signal;
• a third transistor coupled to the first node for conducting a second portion of the first summation current;
• and
• a fourth transistor coupled to the second node for conducting a second portion of the second summation current.

A circuit for modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M, comprising:

• N number of multiplier circuits, each multiplier circuit having multiply means for multiplying one phase of the first waveform with one phase of the second waveform and for generating first and second currents having a difference which is proportional to a product of the one phase of the first waveform and the one phase of the second waveform;
• a load circuit, coupled to the multiplier circuits, havin a first node into which the first currents generated by each of the multiplier circuits are summed together to form a first summation current and a second node into which the second currents generated by each of the multiplier circuits are summed together to form a second summation current, the load circuit having a comparing stage for comparing which of the first and second summation currents is larger and for generating a first clock signal having a frequency approximately equal to a frequecy of a change in magnitude of the first and second summation currents;
• and
• N number of limited swing driver circuits, each limited swing driver circuit having generator means for generating the one phase of the first waveform in response to one phase of a third N-phase waveform having a frequency F.sub.O and for generating the one phase of the first waveform to have a voltage swing that is less than a voltage swing of the third waveform.

A circuit for modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M, comprising:

• N number of limited swing driver circuits, each limited swing driver circuit having generator means for generating one phase of a third waveform in response to one phase of the first waveform so that the third waveform has a frequency F.sub.0 and a voltage swing that is less than a voltage swing of the first waveform;
• N number of multiplier circuits, each multiplier circuit coupled to one of the limited swing driver circuits and having multiply means for multiplying one phase of the third waveform with one phase of the second waveform and for generating first and second currents having a difference which is proportional to a product of the one phase of the third waveform and the one phase of the second waveform;
• and
• a load circuit, coupled to the multiplier circuits, having a first node into which the first currents generated by each of the multiplier circuits are summed together to form a first summation current and a second node into which the second currents generated by each of the multiplier circuits are summed together to form a second summation current, the load circuit having a comparing stage for comparing which of the first and second summation currents is larger and for generating a first clock signal having a frequency approximately equal to a frequency of a change in magnitude of the first and second summation currents.

A modulation circuit, comprising:

• N number of limited swing driver circuits, each limited swing driver circuit having a first CMOS inverter having an output at which one phase of a first N-phase waveform having a frequency F.sub.O is generated, each limited swing driver circuit having means for partially turning on the first CMOS inverter in response to one phase of an N-phase second waveform having a frequency F.sub.O in order to generate the one phase of the first N-phase waveform so that it has a voltage swing that is less than a voltage swing of the one phase of the N-phase second waveform;
• N number of multiplier circuits, each multiplier circuit coupled to one of the limited swing driver circuits and having multiply means for multiplying one phase of the first N-phase waveform with one phase of a third N-phase waveform having a frequency F.sub.M and for generating first and second currents having a difference which is proportional to a product of the one phase of the first N-phase waveform and the one phase of the third N-phase waveform;
• and
• a load circuit, coupled to the multiplier circuits, having a first node into which the first currents generated by each of the multiplier circuits are summed together to form a first summation current and a second node into which the second currents generated by each of the multiplier circuits are summed together to form a second summation current, the load circuit having a first transistor coupled to the tirst node for conducting a tirst portion of the first summation current, a second transistor coupled to the second node for conducting a first portion of the second summation current, and a current difference amplifier coupled to the first and second transistors for converting a difference between the first portion of the first summation current and the first portion of the second summation current into a first clock signal having a frequency approximately equal to a frequency of a change in magnitude of the first and second summation currents.

A method of modulating an N-phase first waveform having a frequency F.sub.O with an N-phase second waveform having a frequency F.sub.M, comprising the steps of:

• generating an N-phase third waveform having a frequency F.sub.O and a voltage swing that is less than a voltage swing of the first waveform;
• multiplying each phase of the third waveform with each respective phase of the second waveform;
• generating first and second currents with respect to each phase of the multiplied third and second waveforms having a difference which is proportional to a product of the respective phases of the third and second waveforms;
• summing together the first currents generated with respect to each phase of the multiplied third and second waveforms to form a first summation current;
• summing together the second currents generated with respect to each phase of the multiplied third and second waveforms to form a second summation current;
• comparing which of the first and second summation currents is larger;
• and
• generating a first clock signal having a frequency approximately equal to a frequency of a change in magnitude of the first and second summation currents.