US 5,708,381 A · Variable delay circuit

Abstract

In a variable delay circuit including a high-speed clock generator receiving a trigger signal and outputting a pulse signal after a desired time interval upon rising of the trigger signal and a coarse delay signal generator, the high-speed clock generator includes a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and outputting an edge detecting pulse having a time interval, and an asynchronous reset oscillator receiving the edge detecting pulse, being reset upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse. The high-speed clock generator of the variable delay circuit is realized without using analog circuits. Further, since the high-speed clock generator includes no PLL, it is not necessary to provide analog circuits, such as charge pump and VCO, in a digital LSI and, therefore, special considerations for the analog circuits are eliminated.

Claims11

Dependent claims

A variable delay circuit comprising:

a high-speed clock generator receiving a trigger signal and outputting a high-speed clock after a time delay upon rising of the trigger signal, the high-speed clock generator comprising:
a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and, in response, outputting an edge detecting pulse having a time interval;
and
an asynchronous reset oscillator receiving the edge detecting pulse, resetting upon rising of the edge detecting pulse, and generating the high-speed clock upon falling of the edge detecting pulse;
and
a coarse delay signal generator receiving the high-speed clock and outputting a coarse delay output, wherein the high-speed clock generator includes a reset pulse generator connected for receiving the edge detecting pulse from the rising edge detector and the high-speed clock from the asynchronous reset oscillator, and outputting a reset signal for resetting the coarse delay signal generator.

3 more elements

A variable delay circuit comprising:

a high-speed clock generator receiving a trigger signal and outputting a high-speed clock after a time delay upon rising of the trigger signal, the high-speed clock generator comprising:
a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and, in response, outputting an edge detecting pulse having a time interval;
and
an asynchronous reset oscillator receiving the edge detecting pulse, resetting upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse, the asynchronous reset oscillator comprising:
an inverter chain having an input terminal and an output terminal and comprising an even number of inverters and an even number of first two-input NOR circuits connected in series, each first two-input NOR circuit having a first input terminal receiving an output from one of the inverters and a second input terminal connected for receiving the edge detecting pulse from the rising edge detector;
and
a second two-input NOR circuit having a first input terminal connected to the output terminal of the inverter chain, a second input terminal connected for receiving the edge detecting pulse from the rising edge detector, and an output terminal connected to the input terminal of the inverter chain, the second two-input NOR circuit outputting the high-speed clock and wherein the inverter chain and the second two-input NOR circuit are connected as a ring oscillator;
and
a coarse delay signal generator receiving the high-speed clock and outputting a coarse delay output.

6 more elements

A variable delay circuit comprising:

a high-speed clock generator receiving a trigger signal and outputting a high-speed clock after a time delay upon rising of the trigger signal, the high-speed clock generator comprising:
a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and, in response, outputting an edge detecting pulse having a time interval;
an asynchronous reset oscillator receiving the edge detecting pulse, resetting upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse, the asynchronous reset oscillator comprising:
delay path selecting means comprising a plurality of first inverter chains, each first inverter chain having an input terminal, an output terminal, and comprising a plurality of first inverters connected in series, and a selector for selecting one of the first inverter chains, the selector having an output terminal and a plurality of input terminals connected to the output terminals of the first inverter chains;
a second inverter chain comprising a plurality of second inverters connected in series and having an output terminal and an input terminal connected to the output terminal of the selector;
and
a two-input NOR circuit having a first input terminal connected to the output terminal of the second inverter chain, a second input terminal connected for receiving the edge detecting pulse from the rising edge detector, and an output terminal connected to the input terminals of the first inverter chains, the NOR circuit outputting the high-speed clock;
and
a coarse delay signal generator receiving the high-speed clock and outputting a coarse delay output, wherein the high-speed clock generator includes a reset pulse generator connected for receiving the edge detecting pulse from the rising edge detector and the high-speed clock from the asynchronous reset oscillator, and outputting a reset signal for resetting the coarse delay signal generator.

6 more elements

A variable delay circuit comprising:

a high-speed clock generator receiving a trigger signal and outputting a high-speed clock after a time delay upon rising of the trigger signal, the high-speed clock generator comprising:
a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and, in response, outputting an edge detecting pulse having a time interval and
an asynchronous reset oscillator receiving the edge detecting pulse, resetting upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse, the asynchronous reset oscillator comprising:
at least one delay path selecting means comprising a plurality of first inverter chains, each inverter chain having an input terminal and comprising a plurality of first inverters connected in series, and a selector for selecting one of the first inverter chains and having an output terminal;
a second inverter chain comprising an even number of second inverters and an even number of first two-input NOR circuits connected in series and having an input terminal connected to the output terminal of the selector, each first two-input NOR circuit having a first input terminal connected to an output terminal of one of the second inverters and a second input terminal connected for receiving the edge detecting pulse from the rising edge detector;
and
a second two-input NOR circuit having a first input terminal connected to an output terminal of the second inverter chain, a second input terminal connected for receiving the edge detecting pulse from the rising edge detector, and an output terminal connected to the input terminal of the delay path selecting means, the second two-input NOR circuit outputting the high-speed clock wherein the delay path selecting means, the second inverter chain, and the second two-input NOR circuit are connected as a ring oscillator;
and
a coarse delay signal generator receiving the high-speed clock and outputting a coarse delay output.

6 more elements

Dependencies are inferred from the claim text.

Variable delay circuit

Life of this patent

Variable delay circuit

Life of this patent

Abstract

Claims11