Test for hold time margins in digital systems

A flip-flop circuit comprising:

• a first NAND gate responsive to a D input to the flip-flop circuit and a first mode control signal for providing a first NAND gate output;
• a second NAND gate responsive to a serial scan input to the flip-flop circuit and a second mode control signal for providing a second NAND gate output;
• an inverter responsive to said first NAND gate output for providing an inverter output;
• first transmission means responsive to said first NAND gate output and said second NAND gate output for providing a first transmission output, said first transmission means output being a replica of said inverter output when said first mode control signal is of a first logical state and said second mode control signal is of a second logical state, and said first transmission means output being of high impedance when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state;
• second transmission means responsive to said first NAND gate output and said second NAND gate output for providing a second transmission means output, said second transmission means output being a replica of said first NAND gate output when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state, and said second transmission means output being of high impedance when said first mode control signal is of a first logical state and said second mode control signal is of a second logical state;
• a clocked D-type flip-flop responsive to said first transmission means output and said second transmission means output;
• whereby (a) said clocked D-type flip-flop is responsive to said first transmission means output when said first mode control signal is of said first logical state and said second mode control signal is of said second logical state, and (b) said clocked D-type flip-flop is responsive to said second transmission means output when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state.