Semiconductor device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYoshihiro Tomita
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Abstract
A semiconductor device is reduced in size and has a highly warp resistant structure. A sealing resin formed by transfer molding covers a whole semiconductor chip including pad electrodes, connecting bumps, an upper surface of a wiring board including a plurality of chip connecting patterns, a side surface of the wiring board, and a peripheral area of a lower surface of the wiring board surrounding an area where external electrode portions are located. The wiring board is substantially coextensive in an area with the semiconductor chip in plan configuration. The area occupied by the external electrode portions is smaller than the area occupied by the chip connecting patterns.
Claims12
A semiconductor device comprising:
- a semiconductor chip having first and second major surfaces, and a plurality of pad electrodes on the second major surface;
- a wiring board having first and second major surfaces, the second major surface of said semiconductor chip facing the first major surface of said wiring board, said wiring board including a plurality of chip connecting patterns arranged on the first major surface of said wiring board in a first array having a first outer dimension extending from one outside edge of said first array to another, opposite outside edge of said first array, and a plurality of external electrode portions arranged on the second major surface of said wiring board in a second array having a second outer dimension extending from one outside edge of said second array to another, opposite outside edge of said second array, respective chip connecting patterns being electrically connected to corresponding external electrode portions and electrically connected to corresponding pad electrodes;
- and
- a resin covering said semiconductor chip including said plurality of pad electrodes, and the first major surface of said wiring board including said plurality of chip connecting patterns, wherein the second outer dimension is smaller than the first outer dimension.
The A semiconductor device comprising;
- a semiconductor chip having first and second major surfaces, and a plurality of pad electrodes on the first major surface;
- a wiring board having first and second major surfaces, the second major surface of said semiconductor chip facing the first major surface of said wiring board, said wiring board including a plurality of chip connecting patterns on the first major surface of said wiring board, surrounding said semiconductor chip, and arranged in a first array having a first outer dimension extending from one outside edge of said first array to another, opposite outside edge of said first array, and a plurality of external electrode portions arranged on the second major surface of said wiring board in a second array having a second outer dimension extending from one outside edge of said second array to another, opposite outside edge of said second array, respective chip connecting patterns being electrically connected to corresponding external electrode portions and electrically connected to corresponding pad electrodes by bonded metal wires bonded to corresponding pads a respective wire bonding points;
- and
- a resin covering said semiconductor chip including said plurality of pad electrodes, the first major surface of said wiring board including said plurality of chip connecting patterns, and the bonded metal wires, wherein
- the second outer dimension is smaller than the first outer dimension, and
- a distance between an end of said wiring board and a wire bonding point nearest that end is shorter than a distance between that end of said wiring board and the external electrode portion nearest that end.
Dependencies are inferred from the claim text.