Power semiconductor device having an active layer

A power IC comprising:

• a support substrate having an insulating surface;
• a semiconductor active layer formed on said substrate, said active layer having a thickness which is set to be 6 mm or less;
• a device isolation layer formed to reach the insulating surface from a surface of said active layer so as to divide said active layer into first, second and third areas insulated and isolated from each other;
• a low-withstand-voltage, pnp-bipolar transistor formed in the first area;
• a high-withstand-voltage, second semiconductor device formed in the second area;
• and
• a low-withstand-voltage, CMOS transistor formed in the third area, said pnp-bipolar transistor comprising:
• a first main well layer of an p-type formed in a surface of said active layer;
• a first sub-well layer of a n-type formed in a surface of said main well layer, said first main well layer under said first sub-well layer having a thickness which is a set to be 1mm or more, said thickness of said active layer and said thickness of said first main well under said first sub-well being set so as to suppress a leakage current at high operating temperatures and maintaining a substantially maximum amplification factor of said pnp-bipolar transistor by passing a current within said active layer and not through a separate low-resistance buried layer;
• a first emitter layer of the p-type formed in a surface of said first sub-well layer;
• a collector electrode formed on a surface of said first main well layer;
• a base electrode formed on a surface of said first sub-well layer;
• and
• an emitter electrode formed on a surface of said first emitter layer.

A power IC comprising:

• a support substrate having an insulating surface;
• a semiconductor active layer formed on said substrate, said active layer having a thickness which is set to be 6 .mu.m or less;
• a device isolation layer formed to reach the insulating surface from a surface of said active layer so as to divide said active layer into first, second and third areas insulated and isolated from each other;
• a low-withstand-voltage, pnp-bipolar transistor formed in the first area;
• a high-withstand-voltage, second semiconductor device formed in the second area;
• and
• a low-withstand-voltage, CMOS transistor formed in the third area,
• said pnp-bipolar transistor comprising:
• a main well layer of the n-type formed in a surface of said active layer;
• emitter and collector layers of the p-type formed in a surface of said main well layer and configured so as to maintain a substantially maximum amplification factor of said pnp-bipolar transistor by passing a current within said active layer and not through a separate low-resistance buried layer;
• a base electrode formed an a surface of said main well layer;
• an emitter electrode formed on a surface of said emitter layer;
• and
• a collector electrode formed on a surface of said collector layer.