Insulated gate semiconductor device and fabrication method therefor

A vertical semiconductor device with an insulated gate structure comprising:

• a semiconductor substrate as a drain region;
• a channel region formed within the semiconductor substrate;
• a source region formed in contact with said channel region;
• and
• a first gate and a second gate formed on one surface side of the semiconductor substrate, said first and second gates being electrically insulated from the semiconductor substrate and having mutually opposing portions;
• wherein:
• first and second channels corresponding to said first and second gates are formed in said channel region by driving said first and second gates so that currents flow through said first and second channels from another surface side of the semiconductor substrate to said one surface side thereof;
• said first gate is provided on one surface of said semiconductor substrate and said second gate is formed within said semiconductor substrate to have a buried portion encased within said semiconductor substrate, said first gate and said buried portion of said second gate extending in substantially parallel directions with respect to said one surface of said semiconductor substrate:
• and
• a region interposed between said first gate and said buried portion of said second gate forms said channel region.