Non-volatile random access memory
AssigneeSharp Kabushiki Kaisha
InventorShigeo Onishi
Life of this patent
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Abstract
A non-volatile random access memory comprises a memory cell including: a MOS transistor having a gate insulation film formed on a semiconductor substrate, a gate electrode, and a pair of impurity diffusion layers; and an MFS transistor having at least a bottom gate electrode, a ferroelectric film, a top electrode, and a pair of impurity diffusion layers, one of the impurity diffusion layers of the MFS transistor being shared with the MOS transistor and connected to a portion of the bottom gate electrode; wherein the MOS transistor is connected to a bit line and a word line, and the MFS transistor is connected to a drive line and a common source line.
Claims8
A non-volatile random access memory which comprises a memory cell including:
- a MOS transistor having a gate insulation film formed on a semiconductor substrate, a gate electrode, and a pair of impurity diffusion regions;
- and
- an MFS transistor having at least a gate insulation film, a bottom gate electrode, a ferroelectric film, a top electrode, and a pair of impurity diffusion regions, the gate insulation film being formed immediately under a portion of the bottom electrode and between the pair of impurity diffusion regions, and one of the impurity diffusion regions of the MFS transistor being shared with the MOS transistor and connected to a portion of the bottom gate electrode so as to apply a voltage to the bottom gate electrode via the impurity diffusion region;
- wherein the MOS transistor is connected to a bit line and a word line, and the MFS transistor is connected to a drive line and a common source line.
A non-volatile random access memory which comprises a memory cell including:
- a MOS transistor portion having a gate insulation film and a bottom gate electrode formed on the semiconductor substrate, and a pair of impurity diffusion regions, said gate insulation film being formed immediately under a portion of the bottom gate electrode and between the pair of impurity diffusion regions;
- a ferroelectric capacitor portion, formed on the MOS transistor portion, having the bottom gate electrode serving as a bottom electrode, a ferroelectric film and a top electrode,
- wherein the bottom gate electrode is connected to one of the impurity diffusion regions so as to apply a voltage to the bottom gate electrode via the impurity diffusion regions.
Dependencies are inferred from the claim text.