Process for providing electrostatic discharge protection to an integrated circuit output pad

A process of providing electrostatic discharge protection to an integrated circuit output pad, comprising the steps of:

• forming an operative NMOS YET in a P-well on a P-type substrate, said operative NMOS FET having a drain electrically connected to said pad, a source electrically connected to a ground potential of said integrated circuit, and a gate for receiving a logic signal internal to said integrated circuit;
• forming an operative PMOS FET in a N-well on said P-type substrate, said operative PMOS FET having a drain electrically connected to said pad, a source electrically connected to a voltage supply potential of said integrated circuit, and a gate for receiving a logic signal internal to said integrated circuit;
• forming a P-type field implant within a P-well on said P-type substrate;
• and
• electrically connecting a P+ region within said P-type field implant to said ground potential of said integrated circuit, such that a parasitic conductive path is formed from said pad to said ground potential, said parasitic conductive path including a parasitic PN junction diode and a parasitic Zener diode, said junction diode having an anode electrically connected to a cathode of said Zener diode, said Zener diode having an anode electrically connected to said ground potential.