Test structure and method for performing burn-in testing of a semiconductor product wafer

A method for testing product integrated circuits using a test structure:

• providing a test structure wherein the test structure is a semiconductor wafer coupled to a plurality of segmented test integrated circuits where the plurality of segmented test integrated circuits are coupled to a signal distribution film;
• placing a product wafer containing product integrated circuits in contact with the signal distribution film;
• stimulating the product integrated circuits via electrical signals provided from the plurality of segmented test integrated circuits to the product integrated circuits via the signal distribution film;
• identifying which product integrated circuits are failing product integration circuits in response to the step of stimulating;
• and
• dicing and packaging for use the product integrated circuits which are not falling product integrated circuits.

A method for manufacturing a test structure, the method comprising the steps of:

• providing a silicon mold;
• forming a dielectric layer on the silicon mold;
• forming product wafer contact openings in the first dielectric layer;
• forming at least one conductive layer of material overlying the first dielectric layer, the at least one conductive layer forming product wafer contact areas through the product wafer contact openings;
• forming additional dielectric layers as are needed to isolate portions of the at least one conductive layer of material;
• defining top portions of the at least one conductive layer of material as test structure contact areas;
• providing segmented test integrated circuits which have a top layer of conductive bumps and a backside;
• attaching segmented test integrated circuits to the test structure contact areas via the conductive bumps of the segmented test integrated circuits;
• attaching a support wafer to the backside of each of the segmented test integrated circuits;
• attaching conductive leads to conductive lead areas of the at least one conductive layer of material;
• and
• removing the silicon mold to expose the product wafer contact areas so that the segmented test integrated circuits can communicate electrical signals through the at least one conductive layer of material to the product wafer contact areas.

A method for forming a multi-chip module, the method comprising the steps of:

• providing a base substrate;
• forming transistors and conductive interconnects on top of the substrate the conductive interconnects having top-level contact areas;
• contacting conductive members of a singulated integrated circuit to the top-level contact areas so that circuitry on the integrated circuit can electrically communicate with the transistors;
• removing a portion of the base substrate to form a remaining base substrate from the base substrate;
• and
• packaging the remaining base substrate, transistors, and singulated integrated circuit in an integrated circuit package which contains conductors that connects to one or more of the singulated integrated circuit or the transistors.