US 5,707,721 A · Methods of forming field effect transistors having oxidation-controlled gate lengths

Abstract

Methods of forming field effect transistors having oxidation-controlled gate lengths include the steps of forming an insulated gate electrode on a face of semiconductor substrate. The gate electrode has exposed ends thereof which define an initial gate length. Source and drain region dopants are then implanted into first portions of the face, using the insulated gate electrode as an implant mask. The implanted first portions of the face and the exposed ends of the insulated gate electrode are then thermally oxidized to form a relatively thick oxide layer. During this step, the implanted dopants are diffused and bird's beak oxide extensions are formed at the upper and bottom corners of the gate electrode. The bird's beak oxide extensions are preferably formed to increase the separation distance between the gate electrode and the source and drain regions and thereby reduce the gate-source/drain capacitance and inhibit parasitic hot electron injection from the drain region. The step of thermally oxidizing the exposed ends of the insulated gate electrode also causes the ends to be consumed and the first portions of the face to become recessed. Thus, during oxidation, the length of the gate electrode can be reduced in a controlled manner and the degree of vertical overlap between the gate electrode and the diffused source and drain region dopants can be reduced to obtain a further reduction in the parasitic gate-source/drain capacitance. In addition, gate lengths having sub-micron dimensions can be achieved without requiring sub-micron photolithographic line widths to define the gate electrode.

Claims15

Dependent claims

A method of forming a field effect transistor, comprising the steps of:

forming an insulated gate electrode having first and second ends defining an initial length thereof, on a face of a semiconductor substrate of first conductivity type;
patterning a nitride layer on the insulated gate electrode, opposite the face;
implanting first source and drain region dopants of second conductivity type into first portions of the face, using the insulated gate electrode as an implant mask;
oxidizing the first portions of the face and the first and second ends of the insulated gate electrode to reduce the length thereof, while simultaneously diffusing the implanted first source and drain region dopants into the substrate to form source and drain region extensions, said source and drain region extensions defining a channel region therebetween extending opposite the insulated gate electrode;
patterning the insulated gate electrode by etching the oxidized first and second ends thereof using the patterned nitride layer as an etching mask, to define oxide spacers at the first and second ends, the oxide spacers having sidewalls which are self-aligned to edges of the patterned nitride layer;
and
implanting second source and drain region dopants of second conductivity type into the first portions of the face, using the oxide spacers as an implant mask.

4 more elements

A method of forming a field effect transistor, comprising the steps of:

forming a first layer of oxide on a face of a semiconductor substrate of first conductivity type;
then
forming a polycrystalline layer of second conductivity type on the first layer of oxide;
then
forming a second layer of oxide on an upper surface of the polycrystalline silicon layer;
then
forming a silicon nitride layer on the second layer of oxide, opposite the polycrystalline layer;
then
forming an insulated gate electrode having an initial length by etching the silicon nitride layer, second layer of oxide and polycrystalline layer of second conductivity type to expose first and second ends thereof, using a mask;
then
implanting first source and drain region dopants of second conductivity type at a first dose level into first portions of the face, using the insulated gate electrode as an implant mask;
then
oxidizing the first portions of the face and the first and second exposed ends of the insulated gate electrode to reduce the length thereof, while simultaneously diffusing the implanted first source and drain region dopants into the substrate to form source and drain region extensions extending laterally in the substrate underneath the insulated gate electrode, said source and drain region extensions defining a channel region therebetween extending opposite the insulated gate electrode;
then
patterning the insulated gate electrode by etching the oxidized first and second ends thereof to define sidewall spacers at the first and second ends and expose recessed first portions of the face, using the etched silicon nitride layer as a etching mask so that the sidewall spacers are self-aligned to the etched silicon nitride layer;
and
implanting second source and drain region dopants of second conductivity type at a second dose level, greater than the first dose level, into the recessed first portions of the face.

14 more elements

Dependencies are inferred from the claim text.

Methods of forming field effect transistors having oxidation-controlled gate lengths

Life of this patent

Methods of forming field effect transistors having oxidation-controlled gate lengths

Life of this patent

Abstract

Claims15