US 5,706,514 AGranted

Distributed execution of mode mismatched commands in multiprocessor computer systems

AssigneeCompaq Computer Corporation

InventorThomas J. Bonola

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Abstract

A technique for handling processor mode mismatched instructions or commands encountered by a CPU within a multiprocessor computer system. During thread execution, if a multimode processor encounters a command or instruction that it cannot execute without shifting modes or mode emulation, it will look for an alternate processor present in the computer system to instead handle the mode mismatched command. If a suitable alternate is found, necessary input parameters including mode reconfiguration information are downloaded to a common memory area accessible to all processors in the system, and the alternate processor is loaded with the starting address of the code that will handle the mismatched command/instruction. The originating processor may suspend thread execution until the alternate processor completes execution. When complete, the alternate processor downloads the results to common memory, and signals its status to the originating processor. Thereafter, the originating processor uploads the results and resumes thread execution if previously suspended.

Claims7

Dependent claims

A method for operating a muliprocessor system, the multiprocessor computer system including a multimode first processor capable configured for operations in a first processing mode, a second processor capable of being configured for operations in a second processing mode incompatible with said first processing mode, means for storing a code vector, and means for storing data and command parameters accessible to both said first and second processors, a method for processing said command encountered by said first processor which cannot be executed while said first microprocessor is in said first processing mode, the method comprising the steps of:

said first processor determining whether said second processor is available for processing said command;
and
if said second processor is available for processing said command, said first processor offloading said command to said second processor, said offloading steps comprising:
said first processor downloading data and command parameters required for successful processing of said command to said storing means;
said first processor placing a code vector pointing to source code necessary to complete processing of said command in said code vector storing means;
said first processor activating said second processor;
said second processor utilizing said stored data and command parameters and said stored code vector to commence processing of said command;
said second processor storing results obtained from processing said command to said data and command parameters storage means;
said second processor notifying said first processor when said command processing is complete;
and
said first processor uploading said stored results for use in a subsequent task when said second processor notification is received.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/610,027Filed 4 Mar 1996
Granted: 6 Jan 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/45533
Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines:…
G06F 9/3877
Concurrent instruction execution, e.g. pipeline or look ahead: using a secondary processor, e.g. coprocessor
G06F 9/3879
Using a secondary processor, e.g. coprocessor: for non-native instruction execution, e.g. executing a command; for Java instruction set
G06F 9/45504
Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines: abstract…

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