US 5,706,489 AGranted

Method for a CPU to utilize a parallel instruction execution processing facility for assisting in the processing of the accessed data

AssigneeInternational Business Machines Corporation

InventorsChi-Hung Chi, Hatem Mohamed Ghafir, Balakrishna Raghavendra Iyer, Inderpal Singh Narang, Gururaj Seshagiri Rao, Bhaskar Sinha

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU do the rest of the operation synchronously, or c) resume the parallel operation in the processor or a hardware assist if an interruption caused the PIE-PF parallel operation to be checkpointed.

Claims13

Dependent claims

A method of operating a processor electronic complex (CEC) containing at least a Central Processing facility (CPU) and a parallel-instruction-execution processing facility (PIE-PF) and a shared memory, comprising the steps of:

initializing by the CPU executing a supervisory program of a PIE parameter block (PPB) for communicating information between the CPU and the PIE-PF for enabling the CPU to control the PIE-PF to share execution of a program of instructions on the same set of data, executing by the CPU a start parallel instruction execution (SPIE) instruction in supervisory state to signal to the PIE-PF if a PIE Queue Element (PQE) assigned to the PIE-PF is available for CPU use in shifting to the PIE-PF execution of the program on a set of data provided to the CPU, but ending the SPIE instruction execution by the CPU if the PQE is busy,
synchronously continuing execution of the SPIE instruction if the PQE is available by setting an address of a control block (PPB) in the PQE and signalling the PIE-PF to examine the PPB for a SPIE processing operation code for controlling a PIE-PF processing operation,
completing execution by the CPU of the SPIE instruction when the CPU has set fields in the PPB for data to be processed by the executing SPIE instruction,
asynchronously executing on the data by the PIE-PF of a SPIE processing operation indicated by an SPIE processing operation code in the PPB after the PIE-PF examines the SPIE processing operation code and PIE processing parameter information in the PPB,
setting by the PIE-PF of status information in the PPB about the PIE-PF processing operation as the PIE-PF completes the processing operation to enable a communication of status of the PIE-PF processing operation to the CPU, and
indicating by the PIE-PF to the CPU of availability of the PQE for CPU use upon completion of the processing operation on the data by the PIE-PF.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/544,496Filed 18 Oct 1995
Granted: 6 Jan 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 9/30076
Arrangements for executing specific machine instructions: to perform miscellaneous control operations, e.g. NOP
G06F 9/3863
Recovery, e.g. branch miss-prediction, exception handling: using multiple copies of the architectural state, e.g. shadow registers
G06F 9/3877
Concurrent instruction execution, e.g. pipeline or look ahead: using a secondary processor, e.g. coprocessor
G06F
Computing and data processing

Family

No related US applications are recorded in the indexed filing history.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key