US 5,706,485 A · Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature

Abstract

A circuit contains a microprocessor die, containing a microprocessor, and a cache memory die, containing a cache memory, for operation in conjunction with the microprocessor. A microprocessor clock and a cache memory clock are generated for operation of the microprocessor and the cache memory, respectively. The microprocessor and cache memory clocks are generated on the microprocessor die, and the cache memory clock is transmitted to the cache memory die. In order to transmit data between the microprocessor die and the cache memory die, clock cycles are designated. The microprocessor clock and the cache memory clock are synchronized to the clock cycles including compensation for the propagation delay between the two dies. The microprocessor includes a stop clock function which halts the cache memory clock and the microprocessor clock on the same clock cycle so that data integrity, in both the microprocessor and cache memory, are maintained. In order to provide functional operation over a range of clock cycle frequencies, the data, from cache memory die, becomes valid on the falling edge of the cache clock signal, and is subsequently sampled, in the same clock cycle, on the rising edge of the microprocessor clock.

Claims23

Dependent claims

A method for synchronizing clock signals in a circuit comprising a plurality of integrated circuit dies including a host die and at least one secondary die, said method comprising the steps of:

generating a first clock signal on said host die;
inverting said first clock signal to generate a second clock signal for each secondary die;
defining a plurality of clock cycles for synchronous data transfer between said host die and said at least one secondary die such that each of said clock cycles begin, in reference to said second clock signal, one half cycle before each of said clock cycles begin, in reference to said first clock signal;
delaying said second clock signal one half clock cycle minus a propagation delay from said host die to a respective one of said plurality of secondary dies;
transmitting said second clock signal to each of said plurality of secondary dies;
receiving said first clock signal and said second clock signal in a stop clock circuit;
and
asserting a stop clock signal to said stop clock circuit to halt said first clock signal and said second clock signal upon termination of the same clock cycle.

5 more elements

In a circuit comprising a plurality of integrated circuit dies including a host die and at least one secondary die, an apparatus for synchronizing clock signals on said plurality of integrated circuit dies, said apparatus comprising:

clock generation means for generating a first clock signal on said host die;
inverter means coupled to said clock generation means to receive said first clock signal from said clock generation means, and for inverting said first clock signal to generate a second clock signal for each secondary die, a plurality of clock cycles being designated for synchronous data transfer between said host die and said at least one secondary die such that each of said clock cycles begin, in reference to said second clock signal, one half cycle before each of said clock cycles begin, in reference to said first clock signal;
delay means coupled to said inverter means for delaying said second clock signal one half clock cycle minus a propagation delay from said host die to a respective one of said plurality of secondary dies;
transmission means coupled to said delay means for transmitting said second clock signal to each of said plurality of secondary dies;
circuit means for receiving said first clock signal and said second clock signal;
and
stop clock means for asserting a stop clock signal to said circuit means to halt said first clock signal and said second clock signal upon termination of the same clock cycle.

4 more elements

a clock oscillator circuit that generates a first clock signal on said host die;
an inverter coupled to said clock oscillator circuit to receive said first clock signal from said clock oscillator circuit, and that inverts said first clock signal to generate a second clock signal for each secondary die, a plurality of clock cycles being designated for synchronous data transfer between said host die and said at least one secondary die such that each of said clock cycles begin, in reference to said second clock signal, one half cycle before each of said clock cycles begin, in reference to said first clock signal;
at least one delay line coupled to said inverter to receive said second clock signal, said at least one delay line for delaying said second clock signal for each secondary die one half clock cycle minus a propagation delay from said host die to a respective said at least one secondary die;
a bus coupling said at least one secondary die to said host die, said bus for transmitting said second clock signal to each of said at least one secondary die;
a stop clock circuit to receive said first clock signal and said second clock signal;
and
stop clock logic to assert a stop clock signal to said stop clock circuit to halt said first clock signal and said second clock signal upon termination of the same clock cycle.

4 more elements

A computer system comprising:

a microprocessor circuit including a stop clock function that generates a stop clock signal;
at least one cache memory;
an interface circuit for coupling said microprocessor circuit to said at least one cache memory for data transfer, said interface circuit comprising:
a clock generation circuit that generates a microprocessor clock at said microprocessor for said microprocessor circuit and that generates at least one cache memory clock for said at least one cache memory by inverting said microprocessor clock, and that synchronizes said microprocessor clock with said at least one cache memory clock, at said at least one cache memory by defining a plurality of clock cycles for data transfer between said microprocessor circuit and said at least one cache memory such that each of said clock cycles begin, in reference to said second clock signal, one half cycle before each of said clock cycles begin, in reference to said first clock signal;
and
a stop clock circuit coupled to said clock generation circuit and said microprocessor circuit, said stop clock circuit for receiving said microprocessor clock, said at least one cache memory clock and a stop clock signal from said microprocessor circuit such that activation of said stop clock signal results in said stop clock circuit halting said microprocessor clock and said cache memory clock upon termination of the same clock cycle.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature

Life of this patent

Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature

Life of this patent

Abstract

Claims23