US 5,706,484 A · Method for eliminating transition direction sensitive timing skews in a source synchronous design

Abstract

A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers, an external I/O clock generator for transmitting the I/O clock signal, and an inverting external I/O clock generator for transmitting the compliment of the I/O clock signal, wherein the data drivers output data synchronous to the I/O clocks and both transmitted clock signals are combined in a receiving component to form a third clock. The receiving component capturing the outputted data synchronous to the third clock. By outputting data signals in the I/O clock domain and using the combination of the transmitted clock signals to synchronize transmission between external components, the computer system ensures that various output conditions that shift the rising or falling edge of a synchronizing clock are adjusted for by the receiving component generating a third clock that selects the later of the rising or falling clock edge between the transmitted clock signals. A set of data signals, the transmitted I/O clock signal, and the transmitted compliment I/O clock signal are generated from similar drivers and share a common power supply plane to further ensure that the data signals are asserted before the clocking edge of the generated third clock.

Claims9

Dependent claims

An integrated circuit having a plurality of functional units and a clock generator for generating a core clock signal and an input/output (I/O) clock signal, said plurality of functional units including a cache coupled to said core clock signal and an I/O unit coupled to said cache, said I/O unit comprising:

a plurality of data blocks coupled to said core clock signal and said I/O clock signal, each of said data block comprising:
a plurality of data bus drivers, each of said data bus drivers including a first input coupled to said cache and a first output synchronized via said I/O clock signal, said data bus driver for receiving data from said functional units and outputting said data external to said integrated circuit via said first output;
a plurality of first I/O clock generators coupled to said I/O clock signal, said first I/O clock generators outputting a first I/O clock signal via an external clock output, wherein said first I/O clock signal follows the timing of said I/O clock signal;
a plurality of second I/O clock generators coupled to said I/O clock signal, said second I/O clock generators outputting a second I/O clock signal via an external clock output, wherein said second I/O clock signal is an inverse of said I/O clock signal and follows the timing of said I/O clock signal;
a common pull-up supply plane coupled between said data bus drivers, said first I/O clock generators, and said second I/O clock generators;
and
a common pull-down supply plane coupled between said data bus drivers, said first I/O clock generator, and said second I/O clock generator.

4 more elements

A method for reducing the timing skews introduced by various output switching conditions that shift the clocking edges of shared clock signals in a source synchronous design, wherein synchronizing clocks and compliments of said synchronizing clocks are combined to synchronize signal transmissions between a plurality of components, said method comprising:

(a) generating a first clock signal within a first component;
(b) transmitting data signals from said first component synchronous with said first clock signal;
(c) transmitting a plurality of first clock signals from said first component to a second component via a plurality of first drivers;
(d) transmitting a plurality of second clock signals from said first component to said second component, wherein each of said second clock signals is a compliment of said first clock signal and is transmitted via a plurality of second drivers;
(e) creating sets of data signals, wherein each of said sets of data signals is associated with a single transmitted first clock signal and a single transmitted second clock signal;
and
(f) synchronously capturing a set of said data signals in said second component with a combination of a transmitted first clock signal and a transmitted second clock signal, wherein both said transmitted first clock signal and said transmitted second clock signal are associated with said set of data signals.

4 more elements

A source synchronous computer system for reducing wait states and delays between components of said source synchronous computer system, comprising:

a first component and a second component, said first component coupled to said second component, wherein said first component generates data that is synchronously captured by said second component, said first component comprising:
a system clock input;
a plurality of first supply output nodes;
a plurality of second supply output nodes;
a first circuit coupled to said system clock input, wherein said first circuit generates a first clock signal and a second clock signal, said first clock signal for synchronizing external data transmissions, said second clock signal for synchronizing internal data transmissions;
a second circuit coupled between said first clock signal, said second clock signal, and a plurality of input nodes, wherein said second circuit receives external data via said input nodes and generates a plurality of internal data signals;
a plurality of m data driver circuits, wherein each of said m data driver circuits generates an external data output signal of said first component synchronized to said first clock signal, wherein each of said data driver circuits is coupled to an internal data signal via a first input, a data output node for outputting said data signal, a first supply node, and a second supply node;
a plurality of n first clock circuits for transmitting n external first clock signals, wherein each of said first clock circuits is coupled to a first supply node, a second supply node, said first clock signal, and a first clock output node for transmitting one of said n external first clock signals;
a plurality of n second clock circuits for transmitting n external compliment clock signals, said n external compliment clock signals being inversions of said first clock signal, wherein each of said second clock circuits is coupled to a first supply node, a second supply node, said first clock signal, and a second clock output node for transmitting one of said n external compliment clock signals;
an external output bus including said data output nodes of said m data driver circuits;
and
a second component comprising:
a plurality of third clock generators for generating a plurality of third clock signals, wherein each of said third clock generators is coupled to an n external clock signal and an n external compliment clock signal, said third clock generator for logically combining said external clock signals and said compliment external clock signals and outputting a third clock signal;
and
a plurality of m receiving circuits for synchronously capturing m data signals from said external output bus, wherein each of said receiving circuits is coupled to a node of said external data bus via a first input and to a third clock signal via a second input.

12 more elements

Dependencies are inferred from the claim text.

Method for eliminating transition direction sensitive timing skews in a source synchronous design

Life of this patent

Method for eliminating transition direction sensitive timing skews in a source synchronous design

Life of this patent

Abstract

Claims9