US 5,706,480 A · Memory device and method for processing digital video signal

Abstract

A memory device for processing a block of digital video signal data comprises a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block, an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block, a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator, a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator, an input/output unit for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller.

Claims21

Dependent claims

A memory device for processing a block of digital video signal data comprising:

a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block from N.times.N to (N+N).times.(N+n), where n.gtoreq.1, the RBA controller including,
an X-axis varying portion for varying an X-axis size of the block from N to (N+n),
an X-state pointer for counting a varied value of a row address (from 1 to N+n) according to an output (N+n) of the X-axis varying portion,
a Y-state pointer for counting a varied value of a column address (from 1 to N+n) according to an internal system clock generated by the X-axis varying portion,
a mode selector for selecting a usage mode according to the varied value counted by the X-state pointer and the varied value counted by the Y-state pointer, and
an internal control signal generator for generating the system control signal to operate the memory device in the selected usage mode;
an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block;
a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator;
a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator;
and
input/output means for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller.

8 more elements

A memory device for processing a block of digital video signal data comprising;

a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block from N.times.N to (N+n).times.(N+n), where n.gtoreq.1, the RBA controller including,
an X-axis varying portion for varying an X-axis size of the block from N to N+n,
an X-state pointer for counting a varied value of a row address (from 1 to N+n) according to an output (N+n) of the X-axis varying portion,
a Y-state pointer for counting a varied value of a column address (from 1 to N+n) according to an internal system clock generated by the X-axis varying portion,
a mode selector for selecting a usage mode according to the varied value counted by the X-state pointer and the varied value counted by the Y-state pointer, and
and internal control signal generator for generating the system control signal to operate the memory device in the selected usage mode;
an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block;
a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator;
a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator;
and
input/output means for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller;
wherein the X-axis varying portion comprises;
an internal clock generator for receiving an external system clock and external control signals to thereby generate block size control signals and the internal system clock;
a counter controller for receiving the block size control signals from the internal clock generator and generating a signal for controlling a counting range of the X-axis state pointer;
and
an X-axis block controller for controlling the internal control signal generator according to the block size control signals generated by the internal clock generator and the varied value counted by the X-state pointer;
wherein the internal clock generator comprises:
a block size selector for receiving the external control signals to thereby generate the block size control signals;
a frequency multiplier for receiving the external system clock and generating multiplied frequencies;
and
a frequency selector for receiving the block size control signals from the block size selector and the multiplied frequencies from the frequency multiplier and producing the internal system clock.

18 more elements

A memory device for processing a block of digital video signal data comprising:

a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block from N.times.N to (N+n1).times.(N+2), where n1.noteq.n2, the RBA controller including,
an X- and Y-axis varying portion for varying an X-axis size of the block from N to (N+n1) and a Y-axis size of the block from N to (N+n2),
an X-state pointer for counting a varied value of a row address (from 1 to N+n1) according to an output (N+n1) of the X- and Y-axis varying portion,
a Y-state pointer for counting a varied value of a column address (from 1 to N+n2) according to an internal system clock generated by the X- and Y-axis varying portion;
a sync clock generator for generating a sync clock in synchronization with an external system clock;
a mode selector for selecting a usage mode according to the varied value counted by the X-state pointer and the varied value counted by the Y-state pointer;
and
an internal control signal generator for generating the system control signal to operate the memory device in the selected usage mode;
an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block;
a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator;
a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator;
and
input/output means for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller.

10 more elements

A memory device for processing a block of digital video signal data comprising:

a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block from N.times.N to (N+n1).times.(N+n2), where n1.noteq.n2, the RBA controller including,
an X- and Y-axis varying portion for varying an X-axis size of the block from N to (N+n1) and a Y-axis size of the block from N to (N+n2),
an X-state pointer for counting a varied value of a row address (from 1 to N+n1) according to an output (N+n1) of the X- and Y-axis varying portion,
a Y-state pointer for counting a varied value of a column address (from 1 to N+n2) according to an internal system clock generated by the X- and Y-axis varying portion,
a sync clock generator for generating a sync clock in synchronization with an external system clock,
a mode selector for selecting a usage mode according to the varied value counted by the X-state pointer and the varied value counted by the Y-state pointer, and an internal control signal generator for generating the system control signal to operate the memory device in the selected usage mode;
an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block;
a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator;
a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator;
and
input/output means for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller;
wherein the X- and Y-axis varying portion comprises:
a block size selector for receiving external X-axis control signals to thereby generate X-axis block size control signals;
a counter controller for receiving the X-axis block size control signals from the block size selector and generating a signal for controlling a counting range of the X-state pointer;
an X-axis block controller for controlling the internal control signal generator according to the X-axis block size control signals generated by the block size selector and the varied value counted by the X-state pointer;
and
a Y-axis block size selector/internal clock generator for receiving the external system clock and external Y-axis control signals to thereby generate Y-axis block size control signals and the internal system clock;
wherein the Y-axis block size selector/internal clock generator comprises:
a Y-axis block size selector for receiving the external Y-axis control signals to thereby generate the Y-axis block size control signals;
a Y-axis frequency multiplier for receiving the external system clock and generating multiplied frequencies;
and
a Y-axis frequency selector for receiving the Y-axis block size control signals from the Y-axis block size selector and the multiplied frequencies from the Y-axis frequency multiplier and producing the internal system clock.

19 more elements

A memory device for processing a block of digital video signal data comprising:

a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block from N.times.N to (N+n1).times.(N+n2), where n1.noteq.n2;
an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block (N+n1).times.(N+n2);
a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator;
a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator;
and
input/output means for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller.

3 more elements

Dependencies are inferred from the claim text.

Memory device and method for processing digital video signal

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Memory device and method for processing digital video signal

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Abstract

Claims21