US 5,706,474 A · Synchronous memory system with asynchronous internal memory operation

Abstract

A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

Claims27

Dependent claims

A memory system comprising:

a plurality of memory blocks;
a synchronous data-transfer circuit for converting serially incoming data having a cycle of a first clock to data having a cycle of a second clock, and serially outputting said data having the cycle of the second clock;
and
a data bus coupled between an input of said synchronous data-transfer circuit and said plurality of memory blocks;
wherein read data from one of said plurality of memory blocks is serially supplied to the input of said synchronous data-transfer circuit via said data bus at the cycle of the first clock;
wherein the read data are serially outputted from said synchronous data-transfer circuit at the cycle of the second clock, and
wherein the first clock is a synchronous to the second clock.

4 more elements

A memory system comprising:

a plurality of memory blocks;
a common control circuit for controlling each of said plurality of memory blocks;
a complementary data bus coupled between said common control circuit and said plurality of memory blocks;
and
a data input terminal coupled to said common control circuit;
wherein said common control circuit converts a serial data supplied from said data input terminal to a pair of complementary serial data using a second clock, and supplies the pair of complementary serial data to said complementary data bus;
and
wherein one of said plurality of memory blocks to which the pair of complementary serial data is transferred extracts an internal clock from the pair of complementary serial data in order to change a write address therein.

5 more elements

Dependencies are inferred from the claim text.

Synchronous memory system with asynchronous internal memory operation

Life of this patent

Synchronous memory system with asynchronous internal memory operation

Life of this patent

Abstract

Claims27