Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs

A method of simulating a circuit on a computer system, said circuit including a computer model of a Finite State Machine (FSM), said computer system including a processor and a memory, said processor being coupled to said memory, said method comprising:

• accessing a textual description of said computer model:
• compiling said textual description of said computer model into a compiled computer model:
• storing said compiled computer model in said memory;
• accessing said compiled computer model;
• accessing a first input value;
• accessing a first delayed input value;
• accessing a first delayed output value;
• and
• executing a simulation program on said processor causing said processor to access a first output value from said computer model using said first input value, said first delayed input value and said first delayed output value, said first output value corresponding to an output value of said circuit.

A method of synthesizing a portion of a circuit from a computer model of a Finite State Machine (FSM) in a computer system, said computer system including a memory and a processor, said memory being coupled to said processor, said memory storing said computer model, said computer implemented method comprising:

• accessing a first set of outputs from said computer model;
• accessing a first set of delayed outputs from said computer model;
• accessing a first set of inputs from said computer model;
• accessing a first set of delayed inputs from said computer model;
• determining a plurality of signal types corresponding to said first set of delayed outputs, said first set of inputs, and said first set of delayed inputs, said determining said plurality of signal types including.
• identifying a first set of synchronous data signal types.
• identifying a first set of asynchronous data signal types.
• identifying a first set of asynchronous reset signal types.
• identifying a first set of asynchronous set signal _types,
• identifying a first set of asynchronous enable signal types,
• identifying a plurality of active levels,
• identifying a plurality of unatenesses,
• identifying a plurality of edge sensitive signal types, and
• identifying a plurality of level sensitive signal types;
• and
• determining a first circuit primitive corresponding to an output of said first set of outputs and a first signal type of said plurality of signal types.