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US 5,706,471 AGranted
I-O register lock for PCI bus
AssigneeIntel Corporation
InventorWilliam T. Futral
Life of this patent
Estimating the term…
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AssigneeIntel Corporation
InventorWilliam T. Futral
Estimating the term…
A computer system having a bus providing signals for determining a next bus transaction; a processor connected to the bus; and a bus device connected to the bus, the bus device having a first register connected to the bus, a first gate connected to the first register through an output of the first gate, and, a multiple access inhibitor unit connected to a first input of the first gate through an output of the multiple access inhibitor unit. In a bus having a bus master and a bus target, a method of preventing access to a memory mapped register in a transaction, having the steps of detecting a STOP signal, a FRAME signal, a IRDY signal, a TRDY signal, and a DEVSEL signal; generating an access enable signal to the memory mapped register when the FRAME signal is not asserted and the IRDY signal, the TRDY signal, and the DEVSEL signal is asserted; generating the access enable signal to the memory mapped register when the DEVSEL signal is not asserted; preventing generation of the access enable signal to the memory mapped register when the FRAME signal, the IRDY signal, the TRDY signal, and the DEVSEL signal are asserted; and preventing generation of the access enable signal to the memory mapped register when the STOP signal and the FRAME signal is asserted.
A computer system comprising:
In a bus having a bus master and a bus target, a method of preventing access to a memory mapped register in a transaction, comprising the steps of:
An apparatus which prevents access to a memory mapped register in a transaction in a bus having a bus master and a bus target, comprising:
Dependencies are inferred from the claim text.