Von Neumann system with harvard processor and instruction buffer
AssigneeVLSI Technology, Inc.
InventorKenneth A. Dockser
Life of this patent
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Abstract
A hybrid Harvard/Von Neumann data processing system utilizes a Harvard architecture processor with a combined data/instruction memory. A dual-port random-access instruction buffer between memory and the processor provides much of the performance enhancement of an instruction cache when used with a RISC instruction set, but at a much lower cost. The resulting system serves as an entry-level computer system of a series of compatible computers, led at the high end by a Harvard processor with full data and instruction caches.
Claims12
A data processing system comprising:
- main memory having contents stored at respective memory addresses, said contents including data and instructions, said main memory having a content port for receiving data and for sending data, said main memory having a content address port for receiving address requests for selecting memory addresses from which to read contents to be transmitted and to which to write received contents;
- a Harvard architecture central processor having a data port through which data transfers from and to said processor are made, a data address port from which data address requests are made, an instruction port at which instructions are received, and an instruction address port from which instruction address requests are made;
- a single-line multi-instruction buffer having plural buffer address locations including a first buffer address location, each of said buffer locations providing for storage of an instruction;
- a hit detector for determining whether an instruction address requested by said processor is represented in said buffer, said hit detector being coupled to said instruction address port;
- control means for controlling the flow of addresses and contents among the foregoing elements, said control means causing a data address transmitted by said processor to be received at said content address port and causing said contents to be transferred between said content port and said data port, said control means causing an instruction stored in said buffer to be transferred to said instruction port when said hit means indicates that the instruction address requested by said processor is represented in said buffer, said control means causing a line of instructions at consecutive main memory addresses beginning with the address of the requested instruction to be transferred in response to an instruction request when said hit means indicates the requested instruction is not represented in said buffer so that said requested instruction is stored at said first buffer address location and so that any remaining instructions of said line are stored at buffer address locations other than said first buffer address location.
A method of managing communication between a Harvard architecture processor and a main memory, said method comprising the steps of:
- determining whether an instruction requested by said processor is in a single-line multi-instruction buffer having plural buffer address locations including a first address location;
- if the requested instruction is in the buffer, providing it to the processor via its instruction port;
- if the requested instruction is not in the buffer, fetching a line of instructions beginning with said requested instruction, storing said requested instruction at said first address location irrespective of the address of the requested instruction in main memory, storing other instructions in said line at buffer address locations other than said first address location, and copying said requested instruction from said buffer to said processor via said instruction port.
Dependencies are inferred from the claim text.