Processor having a variable number of stages in a pipeline

A processor having a variable stage number pipeline comprising:

• register means for registering operand data;
• instruction fetch means for fetching an instruction from a memory accessed by the processor, in an instruction fetch stage executable in parallel with other stages;
• instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
• instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
• memory access means for accessing for a read/write operation said memory at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
• write back means for writing into said register means either operand data obtained from said memory in said memory access stage or operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
• a pipeline having
• instruction fetch stage data retaining means for retaining data for use in said instruction fetch stage,
• instruction decode stage data retaining means for retaining data for use in said instruction decode stage,
• instruction execute stage data retaining means for retaining data for use in said instruction execute stage,
• memory access stage data retaining means for retaining data for use in said memory access stage, and
• write back stage data retaining means for retaining data for use in said write back stage;
• and
• an instruction fetch stage split means for splitting said instruction fetch stage data retaining means into
• instruction address output stage data retaining means for retaining data for use in said instruction address output stage in which an instruction address is outputted to said memory, and
• instruction data input stage data retaining means for retaining data for use in said instruction data input stage in which data corresponding to said instruction address is inputted from said memory.

A processor having a variable stage number pipeline comprising:

• first memory means for storing an instruction and operand data;
• register means for registering said operand data;
• instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
• instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
• instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
• memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
• write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
• and
• memory access stage split means for splitting said memory access to stage into
• an operand address output stage for outputting to said memory means an operand address and
• an operand data read/write stage for accessing said memory means for reading/writing operand data corresponding to said operand address.

A variable pipeline controller comprising:

• first memory means for storing an instruction and operand data;
• register means for registering said operand data;
• instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
• instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
• instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
• memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
• write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
• a pipeline having
• memory access stage data retaining means for retaining data for use in said memory access stage,
• instruction decode stage retaining means for retaining data for use in said instruction decode stage,
• instruction execute stage data retaining means for retaining data for use in said instruction execute stage,
• memory access stage data retaining means for retaining data for use in said memory access stage, and
• write back stage data retaining means for retaining data for use in said write back stage;
• and
• memory access stage split means for splitting said memory access stage data retaining means into
• operand address output stage data retaining means for retaining data for use in said operand address output stage for outputting to said first memory means an operand address, and
• an operand data read/write stage data retaining means for retaining data for use in said operand data read/write stage for accessing said first memory means for reading/writing operand data corresponding to said operand address.

A variable length pipeline controller comprising:

• first memory means for storing an instruction and operand data;
• register means for registering said operand data;
• instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
• instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
• instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
• memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
• write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
• instruction fetch stage split means for splitting said instruction fetch stage into
• an instruction address output stage for outputting to said first memory means an instruction address, and
• an instruction data input stage for inputting from said first memory means input data corresponding to said instruction address;
• and
• memory access stage split means for splitting said memory access stage into
• an operand address output stage for outputting to said first memory means an operand address, and
• an operand data read/write stage for accessing said first memory means for reading/writing operand data corresponding to said operand address.

A variable length pipeline controller comprising:

• first memory means for storing an instruction and operand data;
• register means for registering said operand data;
• instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
• instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
• instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
• memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
• write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
• a pipeline having
• instruction fetch stage data retaining means for retaining data for use in said instruction fetch stage,
• instruction decode stage data retaining means for retaining data for use in said instruction decode stage,
• instruction execute stage data retaining means for retaining data for use in said instruction execute stage,
• memory access stage data retaining means for retaining data for use in said memory access stage, and
• write back stage data retaining means for retaining data for use in said write back stage;
• instruction fetch stage split means for splitting said instruction fetch stage data retaining means into
• instruction address output stage data retaining means for retaining data for use in said instruction address output stage for outputting to said first memory means an instruction address, and
• instruction data input stage data retaining means for retaining data for use in said instruction data input stage for inputting from said first memory means input data corresponding to said instruction address;
• and
• memory access stage split means for splitting said memory access stage data retaining means into
• operand address output stage data retaining means for retaining data for use in said operand address output stage for outputting to said first memory means an operand address, and
• an operand data read/write stage data retaining means for retaining data for use in said operand data read/write stage for accessing said first memory means for reading/writing operand data corresponding to said operand address.

A pipeline processing method for use in a processor apparatus having a pipeline function, comprising:

• an instruction address output stage of outputting an address for fetching a first instruction;
• an instruction data input stage of outputting an address for fetching a second instruction and of inputting data at said first instruction;
• an instruction decode stage of decoding said first instruction inputted in said instruction data input stage;
• an instruction execute stage of executing said first instruction decoded in said instruction decode stage;
• a memory access stage of either reading or writing data at an address calculated from said first instruction executed in said instruction execute stage, when said first instruction is an instruction for either one of reading from and writing to a memory said operand data;
• and
• a write back stage of writing data into an register, when said first instruction is an instruction for writing said data into said register.

A pipeline process method for use in a processor apparatus having a pipeline function, comprising:

• an instruction fetch stage of fetching a first instruction;
• an instruction decode stage of decoding said first instruction fetched in said instruction fetch stage;
• an instruction execute stage of executing said first instruction decoded in said instruction decode stage;
• an operand address output stage for outputting an address calculated from said first instruction executed in said instruction execute stage;
• an operand data read/write stage of outputting an address calculated by executing a second instruction, when said second instruction is an instruction for either one of reading from and writing to a memory said operand data;
• and
• a write back stage of writing data into a register, when said first instruction is an instruction for writing said data into said register.

A pipeline processing method for use in a processor apparatus having a pipeline function, comprising:

• an instruction address output stage of outputting an address for fetching a first instruction;
• an instruction data input stage of outputting an address for fetching a second instruction and of inputting data on said first instruction;
• an instruction decode stage of decoding said first instruction inputted in said instruction address input stage;
• an instruction execute stage of executing said first instruction decoded in said instruction decode stage;
• an operand address output stage for outputting an address calculated from said first instruction executed in said instruction execute stage;
• an operand data read/write stage of outputting an address calculated by executing a second instruction, when said second instruction is an instruction for either one of reading from and writing to a memory operand data;
• and
• a write back stage of writing data into a register, when said first instruction is an instruction for writing said data into said register.

A variable stage number pipeline controller for use in a processor comprising:

• instructions fetch means for fetching an instruction from a memory accessed by the processor, in an instruction fetch stage executable in parallel with other stages;
• instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
• instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
• memory access means for accessing for a read/write operation said memory at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
• write back means for writing into a register equipped with the processor either operand data obtained from said memory in said memory access stage or operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
• and
• instruction fetch stage split means for splitting said instruction fetch stage into an instruction address output stage in which the instruction fetch means outputs to said memory an instruction address, and an instruction data input stage in which the instruction fetch means is inputted from said memory input data corresponding to said instruction address.