US 5,706,369 A · Base-n resolution converter

Abstract

A resolution conversion system for real-time expansion and reduction of a first plurality of input pixels into a second plurality of output pixels. The resolution conversion system comprises a base-n counter for counting input pixels as each pixel is captured. The base-n counter has a plurality of carry out signals. Also, there is a control register for selectively enabling the carry out signals of the base-n counter based on a predetermined resolution ratio between the first plurality of input pixels and the second plurality of output pixels. The control register uses a mode bit to select either one of inserting and removing operations. An inserting logic unit is used for inserting, as indicated by the mode bit, a pixel into the plurality of input pixels upon a transition of one of the carry out signals if the carry out signals have been enabled by the control register. A removing logic unit is used for removing, as indicated by the mode bit, a pixel from the plurality of input pixels upon a transition of one of the carry out signals of the base-n counter if the carry out signals have been enabled by the control register.

Claims23

Dependent claims

A resolution conversion system for real-time modification of a first plurality of input pixels serially captured by a predetermined signal into a second plurality of output pixels, comprising:

a base-n counter for counting said first plurality of input pixels as each pixel is serially captured by said predetermined signal, the base-n counter having a plurality of carry out signals to indicate, when selectively enabled, whether a pixel in said first plurality of input pixels is to be modified;
control register for selectively enabling said carry out signals of said base-n counter based on a base-n difference as represented by a ratio between said second plurality of output pixels and said first plurality of input pixels, said control register also comprising a mode bit to select either one of inserting and removing operations;
pixel modifying means, responsive to said mode bit, for serially modifying said pixel by either inserting or removing, upon a transition of one of said carry out signals selectively enabled by said control register.

A resolution conversion system for real-time serial expansion and reduction of a first plurality of input pixels serially captured by a predetermined signal into a second plurality of output pixels, comprising:

a base-n counter for counting said predetermined signal as a current pixel from said plurality of input pixel is serially captured and generating a predetermined number of carry-out signals as it counts in base-n;
a control register coupled to said base-n counter for selectively enabling said predetermined number of carry-out signals from said base-n counter based on a base-n representation of a base-n difference as represented by a ratio between said first plurality of input pixels and said second plurality of output pixels;
pixel modify means coupled to said base-n counter and said control register for serially modifying said current pixel, said pixel modify means capturing said current pixel and its corresponding predetermined signal, said pixel modify means modifying said current pixel upon a transition at one of said carry-out signals said carry-out signal having been selectively enabled by said control register.

Dependencies are inferred from the claim text.

Base-n resolution converter

Life of this patent

Base-n resolution converter

Life of this patent

Abstract

Claims23