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US 5,706,296 AGranted
Bi-directional scan design with memory and latching circuitry
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
A scan cell (51) for use at an input/output terminal includes memory circuitry (Mem 1) for storing test data from a test data path, and a latching circuit (S4, LOB; S6, LIB) connected to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry. The input/output terminal has an input buffer (IB) and an output buffer (3SOB) associated therewith, and the latching circuit includes one of the input buffer and the output buffer.
Claims19
An electrical circuit, comprising:
- functional circuitry for performing normal operating functions of the electrical circuit;
- a terminal which is accessible externally of said electrical circuit;
- an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal;
- an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal;
- a test data path for providing test data;
- memory circuitry coupled to said test data path for storing test data received from said test data path;
- and
- a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including one of said input buffer and said output buffer.
5 more elements
An electrical circuit, comprising:
- functional circuitry for performing normal operating functions of the electrical circuit;
- a terminal which is accessible externally of said electrical circuit;
- an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal;
- an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal;
- a test data path for providing test data;
- memory circuitry coupled to said test data path for storing test data received from said test data path;
- and
- a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer.
5 more elements
An electrical circuit, comprising:
- functional circuitry for performing normal operating functions of the electrical circuit;
- a terminal which is accessible externally of said electrical circuit;
- an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal;
- an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal;
- a test data path for providing test data;
- memory circuitry coupled to said test data path for storing test data received from said test data path;
- and
- a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said output buffer, and said latching circuit operable to resolve voltage contention at said externally accessible terminal.
5 more elements
An electrical circuit, comprising:
- Functional circuitry for performing normal operating functions of the electrical circuit;
- a terminal which is accessible externally of said electrical circuit;
- an input buffer coupled to said functional circuitry and said externally accessible terminal for driving into said functional circuitry input signals received at said externally accessible terminal;
- an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal;
- a test data path for providing test data;
- first memory circuitry coupled to said test data path for storing test data received from said test data path;
- a first latching circuit connected to said first memory circuitry for receiving and selectively latching test data stored in said first memory circuitry, said first latching circuit including said input buffer;
- second memory circuitry coupled to said test data path for storing test data received from said test data path;
- and
- a second latching circuit connected to said second memory circuitry for receiving and selectively latching test data stored in said second memory circuitry, said second latching circuit including said output buffer.
7 more elements
An electrical circuit, comprising:
- functional circuitry for performing normal operating functions of the electrical circuit;
- a terminal which is accessible externally of said electrical circuit;
- an output buffer coupled to said functional circuitry and said externally accessible terminal for receiving output signals from said functional circuitry and driving said output signals to said externally accessible terminal;
- an input buffer having an input and an output, said input coupled to said externally accessible terminal for driving to said output signals received at said externally accessible terminal;
- a test data path for providing test data;
- memory circuitry coupled to said test data path for storing test data received from said test data path;
- and
- a latching circuit connected to said memory circuitry for receiving and selectively latching test data stored in said memory circuitry, said latching circuit including said input buffer and said output buffer.
5 more elements
Dependencies are inferred from the claim text.