Method of testing single-order address memory

A method of testing a single-order address memory having N memory cells and N mutually different addresses in the memory, said method comprising:

• (a) creating a plurality of test vectors each having N bits of data, where M is the number of consecutive bits in each vector having the same state, including:
• (1) defining a first vector in which each bit is 0;
• (2) defining another vector in which the first M2 bits in each group of M bits in the previously defined vector is set to 0 and the second group of M2 bits in each group is set to 1;
• and
• (3) repeating step (2) until log.sub.2 N+1 vectors are created;
• (b) selecting one of the vectors;
• (c) writing the selected vector into each memory cell, including:
• writing the first bit of the selected vector into each location of a first one of said memory cells;
• and
• writing each successive bit of the selected vector into each location of a different one of said memory cells;
• (d) reading data stored at each address;
• (e) writing the inversion of the selected vector into each memory cell, including:
• writing the first bit of the inversion of the selected vector into each location of the first one of said memory cells;
• and
• writing each successive bit of the inversion of the selected vector into each location of a different one of said memory cells;
• (f) reading data stored at each address;
• (g) writing the selected vector into each memory cell;
• (h) reading data stored at each address;
• and
• (i) performing steps (c) through (h) with each of the remaining test vectors.