Data module with variable data word length for a serial multiplex data system
AssigneeSquare D Company
InventorRobert E. Riley
Life of this patent
Estimating the term…
Abstract
A programmable data link module for use with a time division multiplex data bus includes a word extender module. The module can receive, send, or receive and send data over the data bus during a preselectable time period. The time period is defined by a programmable starting address and an ending address. The data can be single or multibit and variable length as determined by the time period selected.
Claims21
In a data link module having means for conveying input data signals at an input terminal to a data bus during a preselected associated one of a plurality of time division multiplex addresses definable by cycles of a master synchronous clock connectable to a clock input terminal, the improvement being an input word extender, comprising:
- means for storing a selected one of the plurality of addresses as a start address;
- means for selecting another one of the addresses independently of the selected one of the plurality of addresses;
- means for storing the other selected one of the plurality of addresses as a stop address selected independently of the start address;
- means for generating a shift clock out signal in synchronization with the master synchronous clock to identify a plurality of addresses between said stored start address and said independently selected stored stop address during the time between occurrence of the start address and the stop address when an input data signal is produced;
- and
- means responsive to the shift clock out signal to cause the input data signal conveying means to convey input data signals to the data bus terminal during each of the addresses between the start and stop address.
In a data link module having means for conveying data at a data bus terminal to an output terminal during a preselectable associated one of a plurality of time division multiplex addresses definable by the cycles of a master synchronous clock connectable to a clock input terminal, the improvement being an output word extender, comprising:
- means for storing a start address;
- means for storing a stop address;
- means for generating a shift clock in signal in synchronization with the master synchronous clock to identify a plurality of addresses between the start and stop addresses during the time between occurrence of the start address and stop address;
- and
- means responsive to the shift clock in signal to cause the input data conveying means to convey data on the data bus to the output terminal during each of the addresses between the start and stop addresses.
A data link module coupled to a data bus and a master clock line for use in a serial time division multiplexing control system having multiple data link modules, the master clock line for generating a predetermined number of time slots for a complete cycle, each time slot in a cycle associated with an address location of one or more data link modules and a data bit on the data bus, the data link module comprising:
- A. an input circuit for receiving data from the data bus at a predetermined time slot, the received data for controlling a plurality of output devices coupling to the data link module;
- B. an output circuit for sending data to the data bus during a predetermined time slot, the data for indicating status for a plurality of input devices coupled to the data link module;
- C. a memory for storing a programmable start address and a stop address of the data link module;
- D. a programmable word extender for producing shift-in clock pulses and shift-out clock pulses in synchronization with the master clock pulse for a predetermined number of time slots, starting when detecting the start address and stopping when detecting the stop address;
- E. wherein the input circuit is responsive to the shift-in clock pulse to receive data from the data bus to control the status of each of the output devices, sequentially one at a time during each of the addresses between the start and stop addresses;
- and
- F. wherein the output circuit is responsive to the shift-out clock pulse to send the status of each of the input devices, sequentially one at a time to the data bus during each of the addresses between the start and stop addresses.
Dependencies are inferred from the claim text.