Address transition detection circuit

An address transition detection circuit comprising:

• an address input circuit for generating an input logic operation signal by a logic operation of a chip select signal and an address signal having a given pulse width;
• a latch circuit for generating first and second latch signals, said latch circuit including first and second NAND gates having first input terminals to which said input logic operation signal and an inverted input logic operation signal are transferred, said latch circuit further including voltage adjusting means for adjusting a voltage of the first input terminals of said first and second NAND gates;
• a feedback circuit having a third NAND gate for generating a first feedback signal by said first and second delay signals, and having a fourth NAND gate for receiving said first feedback signal and said first and second latch signals and generating a second feedback signal;
• first and second delay circuits for generating said first and second delay signals by delaying said first and second latch signals for a prescribed delay time;
• and
• an address transition detection signal output circuit for receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time of said first or second delay circuit when said address signal is changed.

An address transition detection device comprising:

• an address input circuit for generating an input logic operation signal by operating on a chip select signal and an address signal having a pulse width;
• a latch circuit for receiving said input logic operation signal and an inverted input logic operation signal and generating first and second latch signals;
• a feedback circuit coupled to said latch circuit for generating first and second feedback signals and controlling said latch circuit;
• first and second delay circuits for generating first and second delay signals by delaying said first and second latch signals generated by said latch circuit for a prescribed delay time;
• and
• an address transition detection signal output circuit for receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time, irrespective of the pulse width of said address signal.

A method of detecting an address transition for a memory device, comprising the steps of:

• generating an input logic operation signal and an inverted input logic operation signal by operating on a chip select signal and an address signal;
• receiving said input logic operation signals and generating first and second latch signals using a latch circuit;
• generating first and second delay signals by delaying said first and second latch signals for a prescribed delay time;
• generating first and second feedback signals by using said first and second delay signals to control said latch circuit;
• and
• receiving said first and second latch signals and said first and second delay signals, and generating an address transition detection signal having a pulse width longer than said prescribed delay time, irrespective of the pulse width of said address signal.