Word line decoding circuit of a semiconductor memory device

A word line decoding circuit of an integrated semiconductor memory device including a plurality of memory cells for storing information, said word line decoding circuit comprising:

• a row decoder that decodes an external address and generates a single row decoding signal, said single row decoding signal being transmitted along an output line which contains a metallic portion and a strap, said output line associated with a plurality of at least four word lines coupled to said plurality of memory cells;
• a plurality of word drive decoders which each generate a complementary word line driving signal and a non-complementary word line driving signal;
• and
• a plurality of word line drivers which are respectively coupled to said plurality of word lines and which form first and second word line driver groups, said plurality of word line drivers arranged so that said plurality of memory cells are formed between said first and second word line driver groups, each of said word line drivers inputting said single row decoding signal output from said row decoder and said complementary word line driving signal and said non-complementary word line driving signal from one of said plurality of word drive decoders and generating a memory cell select signal along one of said plurality of word lines.

A word line decoding circuit of an integrated semiconductor memory device including a plurality of memory cells for storing information, said word line decoding circuit comprising:

• a row decoder that decodes an external address and generates a single row decoding signal, said single row decoding signal being transmitted along an output line which contains a metallic portion and a strap, said output line associated with a plurality of at least four word lines coupled to said plurality of memory cells;
• a plurality of word drive decoders which each generate a word line driving signal;
• and
• a plurality of word line drivers which are respectively coupled to said plurality of word lines and which form first and second word line driver groups, said plurality of word line drivers arranged so that said plurality of memory cells are formed between said first and second word line driver groups, each of said first and second word line driver groups inputting said single row decoding signal output from said row decoder and certain of said word line driving signals from certain of said plurality of word drive decoders and generating memory cell select signals along some of said plurality of word lines.

A word line decoding circuit of an integrated semiconductor memory device including a plurality of memory cells formed in a memory cell area, a first strap area adjacent one side of said memory cell area, and a second strap area adjacent a side opposite said one side of said memory cell area, said word line decoding circuit comprising:

• a row decoder that decodes an external address and generates a single row decoding signal, said single row decoding signal being transmitted along an output line having a metallic portion formed over said memory cell area, and straps formed in said first and second strap area, said output line associated with a plurality of at least four word lines coupled to said plurality of memory cells;
• a plurality of word drive decoders which each generate a complementary word line driving signal and a non-complementary word line driving signal;
• and
• a plurality of word line drivers which form first and second word line driver groups, said first driver group arranged adjacent said first strap area, and said second driver group arranged adjacent said second strap area, so that said plurality of memory cells are formed between said first and second word line driver groups, each of said word line drivers inputting said single row decoding signal output from said row decoder and said complementary word line driving signal and said non-complementary word line driving signal from one of said plurality of word drive decoders and generating a memory cell select signal along one of said plurality of word lines.