Eeprom semiconductor memory device including circuit for generating a voltage higher than a power supply voltage
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Nakamura, Toru Tanzawa
Life of this patent
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Abstract
A semiconductor memory device comprising a memory cell array of a plurality of memory cells formed and arranged on either a semiconductor substrate or a well of a first conductivity type formed on said semiconductor substrate, a plurality of voltage generating circuits for applying said memory cells voltages that are higher than the power supply voltage and different from each other and a switching circuit for selectively connecting the output nodes of said plurality of voltage generating circuits.
Claims70
A semiconductor memory device comprising:
- a semiconductor substrate;
- a memory cell array having a plurality of memory cells formed on one of said semiconductor substrate and a first conductive well formed on said semiconductor substrate;
- a plurality of voltage generating circuits for applying voltages to said plurality of memory cells, said voltages being higher than a power supply voltage and different from each other;
- and
- a switching circuit for connecting each of output nodes of said plurality of voltage generating circuits to said plurality of memory cells.
A semiconductor memory device comprising:
- a memory cell array of a plurality of memory cells formed and arranged on a semiconductor substrate;
- a first voltage generating circuit for applying a first voltage V.sub.1 higher than the power supply voltage to said memory cells;
- a second voltage generating circuit for applying a second voltage V.sub.2 higher than the power supply voltage to said memory cells;
- a third voltage generating circuit for applying a third voltage V.sub.3 higher than the power supply voltage to said memory cells;
- and
- a exchange circuit for connecting said first and second voltage generating circuits in series and the output of said series circuit to the output node of said third voltage generating circuit.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged on a semiconductor substrate;
- and
- a pump circuit having first and second output nodes for providing a predetermined voltage to said plurality of memory cells, wherein
- said pump circuit has at least first and second voltage generating circuits, each having first and second output terminals,
- the second output terminals of said first and second voltage generating circuits are connected respectively to said second output nodes,
- the first output terminal of said first voltage generating circuit is connected to said first output node, and
- the first output terminal of said second voltage generating circuit is connected to the input terminal of said first voltage generating circuit.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in matrix on a semiconductor substrate;
- and
- a pump circuit having a plurality of output nodes and outputs a predetermined voltage to said plurality of memory cells, wherein
- said pump circuit has a different structure when a different node among said plurality of output nodes outputs a voltage.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in matrix on a semiconductor substrate;
- and
- a pump circuit having a plurality of output nodes and outputs a predetermined voltage to said plurality of memory cells, wherein
- said pump circuit has a different number of stages when a different node among said plurality of output nodes outputs a voltage.
Dependencies are inferred from the claim text.