Self-restore circuit with soft error protection for dynamic logic circuits

A method of restoring an output line of a dynamic logic circuit;

• said dynamic logic circuit including a first transistor and a second transistor coupled in series between said output line and a reference voltage node, comprising the steps of:
• evaluating the output line of said dynamic logic circuit;
• activating said first transistor in response to the discharge of said output line;
• and
• activating said second transistor only after activation of said first transistor, in response to an indication that the evaluation cycle is complete.

A memory device comprising:

• a memory cell array having a plurality of memory cells, said memory cells being arranged at positions where a plurality of bit lines cross a plurality of word lines;
• a selection signal for selecting one of said memory cells in accordance with a data writing or reading operation;
• and
• a restore circuit for restoring said memory device, including:
• an output line of said memory device, wherein said output line discharges after an evaluation cycle;
• first transistor and a second transistor connected in series between said output line and a reference voltage node, wherein said first transistor is activated after an evaluation of said output line, and said second transistor is only activated subsequent to activation of said first transistor in response to an indication that the said evaluation cycle is complete;
• and
• means for restoring said output line of said memory device in response to activation of said first transistor and said second transistor.