Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory cells for storing information;
• a pair of bit lines connected to said plurality of memory cells;
• a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
• a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier including a current supply circuit for outputting a second pair of current signals based on the amount of said first pair of current signals of said presense amplifier, and a converting circuit, connected to said current supply circuit, for converting said second pair of current signals from said current supply circuit to said pair of voltage signals in correspondence with a ratio of said second pair of current signals and outputting said pair of voltage signals;
• a write amplifier, connected to said pair of bit lines, for amplifying and outputting write data to said pair of bit lines to be written in said plurality of memory cells;
• and
• write drivers connected to said pair of bit lines and between said presense and main sense amplifiers on one side and the write amplifier on another side, for selectively enabling transmission of said write data from said write amplifier pair of bit lines.

A semiconductor memory device comprising:

• a plurality of memory cells for storing information;
• a pair of bit lines connected to said plurality of memory cells;
• a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
• and
• a main sense amplifier for amplifying said first pair of current signals from the presense amplifier, for outputting a pair of voltage signals in proportion to a ratio of said first pair of current signals, said main sense amplifier further comprising;
• a current supply circuit including
• a high-voltage power supply,
• a first pair of NPN transistors,
• a first constant-current power supply, and
• said first pair of NPN transistors having respective bases supplied with a reference voltage and respective emitters connected to said first constant-current power supply, for providing the output current to said presense amplifier from said emitters of said first pair of NPN transistors and for outputting a second pair of current signals from said respective emitters of said first pair of NPN transistors;
• and
• a converting circuit including
• a second pair of NPN transistors,
• a second constant-current power supply,
• first and second resistors having a same resistance as one another, and
• said second pair of NPN transistors having respective emitters connected together to said second constant-current power supply, respective collectors connected respectively via said first and second resistors to a high-voltage power supply, and bases supplied with said second pair of current signals output from said current supply circuit, for converting said second pair of current signals to said pair of voltage signals respectively output from said respective collectors of said second pair of NPN transistors in correspondence with a ratio and regardless of amplitudes of said second pair of current signals.

A semiconductor memory device comprising:

• a plurality of memory cells for storing information;
• a pair of bit lines connected to said plurality of memory cells;
• a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
• a main sense amplifier for amplifying said first pair of current signals from the presense amplifier, for outputting a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier further comprising;
• a current supply circuit including
• a high-voltage power supply,
• a first pair of NPN transistors,
• a first constant-current power supply, and
• said first pair of NPN transistors having respective bases supplied with a reference voltage and respective emitters connected to said first constant-current power supply, for providing the output current to said presense amplifier from said emitters of said first pair of NPN transistors and for outputting a second pair of current signals from said respective emitters of said first pair of NPN transistors;
• and
• a converting circuit including
• a second pair of NPN transistors,
• a second constant-current power supply,
• first and second resistors having a same resistance as one another, and
• said second pair of NPN transistors having respective emitters connected together to said second constant-current power supply, respective collectors connected respectively via said first and second resistors to a high-voltage power supply, and bases supplied with said second pair of current signals output from said current supply circuit, for converting said second pair of current signals to said pair of voltage signals respectively output from said respective collectors of said second pair of NPN transistors in correspondence with a ratio of said second pair of current signals;
• a bit line equalizer connected to said pair of bit lines and between said plurality of memory cells on one side and said presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said bit lines are not selected;
• a block of pairs of bit lines containing said pair of bit lines;
• a block equalizer connected to said pair of bit lines between said plurality of memory cells on one side and the presense and main sense amplifiers on another side, to reset potentials of said bit lines to a same potential when said block containing said pair of bit lines is not selected;
• a write amplifier, connected to said pair of bit lines, for amplifying and outputting write data to said pair of bit lines to be written in said plurality of memory cells;
• and
• write drivers connected to said pair of bit lines and between said presense and main sense amplifiers on one side and the write amplifier on another side, for selectively enabling transmission of said write data from said write amplifier pair of bit lines.

A semiconductor memory device, comprising:

• a plurality of memory cells storing information;
• a pair of bit lines connected to said plurality of memory cells, said pair of bit lines forming a potential difference based upon said information;
• a presense amplifier detecting the potential difference between said pair of bit lines and outputting a pair of current signals in accordance with the potential difference;
• and
• a main sense amplifier amplifying said pair of current signals from said presense amplifier and converting said pair of current signals to output voltage signals based upon a ratio of said pair of current signals, said main sense amplifier comprising;
• a current supply circuit suppressing variations in said pair of current signals and, in response to said pair of current signals, outputting a pair of output current signals, and
• a converting circuit converting said pair of output current signals to said output voltage signals based upon a ratio of said output current signals.

A semiconductor memory device, comprising:

• a plurality of memory cells storing information;
• a pair of bit lines connecting to said plurality of memory cells, said pair of bit lines forming a potential difference based upon said information;
• a presense amplifier detecting the potential difference between said pair of bit lines and generating a first pair of current signals in accordance with the potential difference;
• and
• a main sense amplifier amplifying said first pair of current signals from said presense amplifier, and comprising;
• a current supply circuit suppressing variations in said first pair of current signals and, in response to said first pair of current signals, outputting a second pair of current signals have a substantially same ratio as said first pair of current signals;
• a converting circuit converting said second pair of current signals to output voltage signals based upon the ratio of said second pair of current signals;
• and
• a level shifter shifting a level of said output voltage signals.

A semiconductor memory device comprising:

• a plurality of memory cells for storing information;
• a pair of bit lines connected to said plurality of memory cells;
• a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
• and
• a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier including
• a current supply circuit for outputting a second pair of current signals based on the amount of said first pair of current signals of said presense amplifier, and
• a differential amplifying circuit having a first pair of transistors with respective bases, said bases connected directly to said presense amplifier to respectively receive said first pair of current signals, and connected to said current supply circuit, for converting said second pair of current signals from said current supply circuit to said pair of voltage signals based upon a difference between said second pair of current signals and outputting said pair of voltage signals.

A semiconductor memory device comprising:

• a plurality of memory cells for storing information;
• a pair of bit lines connected to said plurality of memory cells;
• a presense amplifier for detecting a potential difference between said pair of bit lines based on said information read from said plurality of memory cells and for outputting a first pair of current signals in accordance with the detected potential difference;
• and
• a main sense amplifier for amplifying said first pair of current signals from said presense amplifier and generating a pair of voltage signals based upon a ratio of said first pair of current signals, said main sense amplifier including
• a first transistor having a first collector directly connected to a voltage source, a first base which receives a reference voltage, and a first emitter which receives a first one of said pair of current signals at a first node,
• a second transistor having a second collector directly connected to the voltage source, a second base which receives the reference voltage, and a second emitter which receives a second one of said pair of current signals at a second node, and
• a differential amplifying circuit having third and fourth transistors with respective emitters connected to each other at a third node, wherein a third base of said third transistor is connected to the second node, and a fourth base of said fourth transistor is connected to the first node.