Memory circuit with switch for selectively connecting an I/O pad directly to a nonvolatile memory cell and method for operating same

An integrated memory circuit operable in a selected one of a test mode and a normal operating mode, said memory circuit including:

• an input/output pad providing an interface between the memory circuit and its external environment;
• an array of memory cells;
• a selection circuit connected to the array and configured to connect a selected one of the memory cells to a first node;
• and
• a test mode switch having a closed state in the test mode and an open state in the normal operating mode, wherein the test mode switch connects the input/output pad directly to the first node in the closed state and isolates the input/output pad from the first node in the open state, said test mode switch including:
• a set of series-connected pass transistors, wherein each pass transistor in the set has a gate that receives a test mode enable signal, and wherein a channel terminal of one pass transistor in the set is connected to a channel terminal of another pass transistor in the set at a second node;
• and
• an isolation circuit connected to said second node, and configured to hold said second node at a fixed supply voltage during the normal operating mode.

A method for operating an integrated circuit, said integrated circuit including component circuits, an input/output pad providing an interface between the integrated circuit and its external environment, and a selection circuit configured to connect a selected one of the component circuits to a first node, said method including the steps of:

• connecting the input/output pad directly with the first node in a test mode of the integrated circuit by placing a switch in a closed state;
• isolating the input/output pad from the first node in a normal operating mode of the integrated circuit by placing the switch in an open state, wherein the switch has an element that is normally nonconductive during the open state but which becomes conductive during said open state in response to at least one state of the integrated circuit;
• and
• asserting an isolation voltage to the switch during the normal operating mode to maintain the switch in the open state during the normal operating mode even when the element becomes conductive during said open state.

A method for operating an integrated memory circuit, said memory circuit including an input/output pad providing an interface between the memory circuit and its external environment, an array of memory cells, and a selection circuit connected to the array and configured to connect a selected one of the memory cells to a first node, said method including the steps of:

• connecting the input/output pad directly with the first node in a test mode of the memory circuit by placing a switch in a closed state;
• isolating the input/output pad from the first node in a normal operating mode of the memory circuit by placing the switch in an open state, wherein the switch has an element that is normally nonconductive during the open state but which becomes conductive during said open state in response to at least one state of the memory circuit;
• and
• asserting an isolation voltage to the switch during the normal operating mode to maintain the switch in the open state during the normal operating mode even when the element becomes conductive during said open state.