Testing and repair of wide I/O semiconductor memory devices designed for testing

A memory device comprising:

• an array of memory cells arranged in rows and columns;
• a row decoder circuit for selecting a first row of memory cells in the array, responsive to a first address;
• a column decoder circuit for selecting a first and a second column of memory cells in the array, responsive to a second address and a first logic state of a test mode signal, the column decoder circuit for selecting the first and not the second column of memory cells, responsive to the second address and a second logic state of a test mode signal, and the column decoder circuit for replacing the first and second columns of memory cells, responsive to the second address, if either column of memory cells is defective;
• a comparison circuit, responsive to the first logic state of the test mode signal and a read signal, for comparing a data bit from the first column of memory cells with another data bit from the second column of memory cells and producing a comparison signal indicating the result of the comparison;
• and
• a data terminal of the device for receiving the comparison signal.

A memory device comprising:

• a plurality data terminals;
• plural sub-arrays of memory cells, each sub-array of memory cells arranged in addressable rows and columns of the memory cells and plural sub-arrays of the memory cells being arranged in sets, each set corresponding to a separate one of the data terminals;
• a row decoder circuit, responsive to a row address, for selecting at least one row of memory cells in each of the sets of sub-arrays at once;
• a column decoder circuit, responsive to a column address, for selecting a plurality of columns of the memory cells in each of the sets of sub-arrays at once;
• and
• a data comparison circuit for comparing a plurality of data bits from each set of sub-arrays, responsive to a test mode signal, the data comparison circuit producing a pass signal at each data terminal corresponding to a set of sub-arrays wherein the plurality of data bits are the same, the data comparison circuit producing a fail signal at each data terminal corresponding to a set of sub-arrays wherein the plurality of data bits are not the same,
• wherein the column decoder circuit is arranged for replacing the plurality of columns of the memory cells with an equal number of columns of redundant memory cells, responsive to the column address, in at least one of the sets of sub-arrays that produced the fail signal.

A method of testing and repairing a semiconductor memory device comprising the steps of:

• providing a plurality of semiconductor memory devices, each semiconductor memory device arranged in rows and columns of memory cells and having a plurality of data terminals;
• providing memory tester having a plurality of data terminals;
• coupling each of the plurality of data terminals of each semiconductor memory device to a separate one of the memory tester data terminals;
• applying a test mode signal to the plurality of semiconductor memory devices, thereby initiating a test mode;
• applying a write signal, an address signal and a plurality of data bits to each of the plurality of semiconductor memory devices at the same time, each of the plurality of semiconductor memory devices replicating the plurality of data bits in a number of memory cells greater than the plurality of data terminals of the each semiconductor memory device;
• applying a read signal and the address signal to the plurality of semiconductor memory devices at the same time, each of the plurality of semiconductor memory devices comparing the data bits from the number of memory cells and producing a pass or fail signal at each of the respective data terminals;
• storing the address and an identity of each data terminal corresponding to each fail signal in the memory tester;
• determining whether a defective group of memory cells corresponding to the each stored fail signal is a defective row or column of memory cells;
• repairing the defective group of memory cells in at least one of the plurality of semiconductor memory devices corresponding to the address and the identity of each data terminal by replacing every group of memory cells corresponding to the address and the identity of each data terminal with an equal number of redundant memory cells.