Semiconductor memory device having a redundant memory cell
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorNobuyuki Kokubo
Life of this patent
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Abstract
NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.
Claims8
A semiconductor memory device having an active mode wherein said device is selected by a chip select signal, and a standby mode wherein said deice is not selected by a chip select signal, comprising:
- a plurality of memory cells arranged in a matrix form of rows and columns;
- a plurality of bit line pairs arranged corresponding to said columns and each being connected to the memory cells in the corresponding column;
- a plurality of word lines arranged corresponding to said rows and each being connected to said memory cells in the corresponding row;
- a plurality of load means each being provided between each bit line of each of said plurality of bit line pairs and a node having a first potential for setting a potential on the corresponding bit line to a predetermined potential, each load means having a first impedance;
- load control means for setting, in the active mode, the impedance of each of said plurality of load means to said first impedance, and setting, in the standby mode, the impedance of each of said plurality of load means to a second impedance larger than said first impedance;
- a column of redundant memory cells provided for replacing a column of memory cells having a defective memory cell;
- and
- means for replacing said column of memory cells having a defective memory cell with said column of redundant memory cells, when an applied column address signal selects said column of memory cells having a defective memory cell, wherein
- all of said word lines are unselected in the standby mode.
A semiconductor memory comprising:
- a plurality of memory cells arranged in a matrix form of rows and columns;
- a plurality of bit line pairs arranged corresponding to said columns and each being connected to the memory cells in the corresponding column;
- a plurality of load means provided between each bit line of each of said plurality of bit line pairs and a node having a first potential for setting a potential on the corresponding bit line to a predetermined potential;
- a column of redundant memory cells provided for replacing a column of memory cells having a defective memory cell;
- and
- load control means for setting an impedance of the load means corresponding to the bit line connected to said column of memory cells replaced with said column of redundant memory cells to exceed an impedance of the load means corresponding to another bit line.
Dependencies are inferred from the claim text.