Internal voltage boosting method and circuit for a semiconductor memory device

An internal voltage boosting circuit of a semiconductor device comprising:

• first signal generating means for generating a first enabling signal in an initial active period of a row address strobe signal;
• second signal generating means for generating a second enabling signal in an initial precharge period of said row address strobe signal;
• level detecting means for generating a detection signal activated when the level of an internal boosted voltage is less than a predetermined level, in response to an active period of said first enabling signal and said row address strobe signal;
• third signal generating means for generating a third enabling signal in response to said detection signal and first enabling signal;
• first boosted voltage generating means for generating a first boosted voltage in response to said third enabling signal;
• and
• second boosted voltage generating means for generating a second boosted voltage in response to said second enabling signal.

A method for operating a semiconductor memory device of the type having a plurality of address lines which require a boosted voltage during a precharge period and during an active period, said method comprising:

• detecting a voltage level during an active period of the memory derive;
• boosting the detected voltage level each time the detected level falls below a predetermined voltage level;
• and
• boosting the voltage level during a precharge period of the memory device.

An internal voltage boosting circuit for a semiconductor memory device comprising:

• a first boosted voltage generator for boosting an internal voltage of said memory device;
• a second boosted voltage generator for boosting said internal voltage;
• a voltage level detector operative to detect said internal voltage;
• a first logic circuit operatively connected to said first generator and to said voltage level detector, said logic circuit activating said first generator when (a) the detected voltage falls below a predetermined voltage and (b) the memory device is in an active state;
• and
• a second logic circuit operatively connected to said second generator, said second logic circuit activating said second generator when said memory device is in a precharge state.