Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a plurality of word lines, each word line connected to the memory cells which are disposed in a corresponding row of said memory cell array;
• a plurality of bit line pairs, each bit line pair having first and second bit lines which are connected to the memory cells in a corresponding column of said memory cell array;
• a plurality of sense amplifiers, each sense amplifier amplifying a potential difference between the bit lines of a corresponding one of said bit line pairs;
• a plurality of activation circuits for activating said plurality of sense amplifiers;
• a data bus for supplying input data to said plurality of memory cells;
• a plurality of storage circuits, each storage circuit associated with a corresponding one of the columns of said memory cell array, for storing the input data supplied from said data bus;
• a plurality of transfer circuits for transferring the input data stored in said storage circuits from said storage circuits to said sense amplifiers;
• and
• a transfer control circuit for controlling said plurality of transfer circuits to simultaneously transfer the input data stored in one or more of said storage circuits to said sense amplifiers;
• wherein said memory cell array is divided into a plurality of sub-arrays each including one or more columns of said memory cell array, each of said plurality of sub-arrays and its corresponding sense amplifiers are formed in a respective area, and at least one activation circuit is provided for each respective sub-arrays and each activation circuit is formed at least partly in an area disposed between an adjacent two of said respective areas.