Double poly split gate PMOS flash memory cell

A semiconductor memory cell comprising:

• an N-type well region having formed therein a P+ source, a P+ drain, and a channel region extending between said P+ source and said P+ drain;
• a first insulating layer overlying said well region;
• a floating gate overlying said first insulating layer;
• a second insulating layer overlying said floating gate;
• and
• a select and control gate overlying said second insulating layer, the select and control gate including an elongated portion which extends over a portion of the source preventing overprogramming of the cell, wherein during programming of said cell holes are accelerated across said channel region and collide with electrons in a depletion region of said drain to result in the generation of hot electrons via impact ionization, said hot electrons being injected into said floating gate of said cell and thereby negatively charging said floating gate, said cell being programmed by applying between approximately 5 and 15 volts to said P+ source and to said N-type well region, grounding said P+ drain, and applying a program voltage which ramps from approximately 0 volts to as high as approximately 15 volts to said select and control gate.