US 5,706,206 A · Method of extracting parasitic capacitance values from the physical design of an integrated circuit

Abstract

A method of extracting parasitic capacitance values from the physical design of an integrated circuit, and more particularly, to a method of extracting lateral coupling and fringing capacitance values from the physical design of an integrated circuit, wherein the integrated circuit comprises multiple layers of conductors, each conductor having one or more lateral edges. The method comprises the steps of identifying each conductor's one or more lateral edges; fragmenting the lateral edges of each conductor into edge fragments based on a number of conductors present in layers above and/or below a given lateral edge; identifying the edge fragments which are laterally adjacent to each edge fragment; computing one or more relationships between an edge fragment and each of its laterally adjacent edge fragments; retrieving parasitic capacitance data for each edge fragment; and using the retrieved parasitic capacitance data to compute one or more parasitic capacitance values for each edge fragment. Disadvantages of prior methods are overcome in that extracted lateral coupling capacitances are based on the presence of conductors running above and/or below a given lateral conductor edge, and fringing capacitances are based on the spacing between a given lateral conductor edge and a laterally adjacent conductor edge.

Claims20

Dependent claims

A method of extracting parasitic capacitance values from a physical design of an integrated circuit (IC) comprising multiple layers of conductors, the method comprising the steps of:

a) identifying one or more lateral edges of each conductor in the IC;
b) for each conductor in the IC, fragmenting its lateral edges into edge fragments based on a number of conductors present in layers above and/or below a given lateral edge;
c) for each edge fragment, identifying its laterally adjacent edge fragments;
d) for each edge fragment, computing one or more relationships between it and each of its laterally adjacent edge fragments;
e) retrieving parasitic capacitance data for each edge fragment;
f) using the parasitic capacitance data of step d), computing one or more parasitic capacitance values for each edge fragment.

3 more elements

Dependencies are inferred from the claim text.

Method of extracting parasitic capacitance values from the physical design of an integrated circuit

Life of this patent

Method of extracting parasitic capacitance values from the physical design of an integrated circuit

Life of this patent

Abstract

Claims20